SDI

270 MBPS DATA

NO DATA

Lock

Detect

SD

T2

NO DATA

270 MBPS DATA

NO DATA

T2

TACQ = Acquisition Time, defined in the AC Electrical Characteristics Table

T1 = Time from Lock Detect assertion or deassertion until SD output is valid, typically 37 ns (one 27 MHz clock period)

T2 = Time from SDI input change until Lock Detect de-assertion, 1 ms maximum. SD output is not valid during this time.

TACQ

T1

T1

TACQ

T1

T1

LMH0026

SNLS253B – MARCH 2008 – REVISED APRIL 2013

www.ti.com

Table 1. Control Functionality

LOCK DETECT

OUTPUT MUTE

BYPASS/AUTO BYPASS

DEVICE STATUS

0

1

X

PLL unlocked, reclocker bypassed

1

1

0

PLL locked to supported data rate, reclocker not bypassed

X

0

X

Outputs muted

0

LOCK DETECT

X

Outputs muted

1

LOCK DETECT

0

PLL locked to supported data rate, reclocker not bypassed

SD

The SD output indicates that the LMH0026 is locked and processing SD data rates. It may be used to control

another device such as the LMH0002 cable driver. When this output is high it indicates that the data rate is 270

Mbps. The SD output is a registered function and is only valid when the PLL is locked and the Lock Detect

output is high. When the PLL is not locked (the Lock Detect output is low), the SD output defaults to low. The SD

output is undefined for a short time after lock detect assertion or de-assertion due to a data change on SDI. See

Figure 4 for a timing diagram showing the relationship between SDI, Lock Detect, and SD.

Figure 4. SDI, Lock Detect, and SD Timing

SCO_EN

Input SCO_EN enables the SCO/SDO2 differential output to function either as a serial data-rate clock or second

serial data output. SCO/SDO2 functions as a serial data-rate clock when SCO_EN is high. This pin has an

internal pull-down device. The default state (low) enables the SCO/SDO2 output as a second serial data output.

CRYSTAL OR EXTERNAL CLOCK REFERENCE

The LMH0026 uses a 27 MHz crystal or external clock signal as a timing reference input. A 27 MHz parallel

resonant crystal and load network may be connected to the XTAL IN/EXT CLK and XTAL OUT pins.

Alternatively, a 27 MHz LVCMOS compatible clock signal may be input to XTAL IN/EXT CLK. Parameters for a

suitable crystal are given in Table 2.

8

Submit Documentation Feedback

Copyright © 2008–2013, Texas Instruments Incorporated

Product Folder Links: LMH0026