PCM1850

PCM1851

SLES108 − MARCH 2004

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15

ANALOG FRONT END

The PCM1850/1851 has a built-in analog front-end circuit, which is shown in the block diagram of Figure 22. Selection of

the multiplexer input and PGA gain is controlled by mode control via the serial port as shown in Table 2 and Table 3. The

change of the input selection and the gain selection is performed immediately after the serial control packet for the change

is sent. A popping noise or other unexpected transient response could be generated in the audio signal during channel and

gain change. Because the PCM1850/1851 has no zero-cross detection and no other buffering capability for channel and

gain change, appropriate data handling in the digital domain is recommended to control transients.

The PCM1850/1851 analog front end permits only ac input via an input capacitor; dc input is prohibited. A signal source

resistance of less than 1 k

Ω is recommended for the VINxx pins.

All unselected channel inputs are terminated VREFS (= 0.5 VCC) using a resistor, typically 57 kΩ.

The PCM1850/1851 employs MOUTL/R pins (pins 12 and 11) to monitor the multiplexer output. The load on these pins

must be ac-coupled and not less than 10 k

Ω. The full-scale output level is typically 0.6 VCC.

PGA

(11 dB to –11 dB)

with MUX

G = –1

VREFS

(= 0.5 VCC)

LIN+

R

VINL1

R

VINL6

R

VINL2

VREF1

(= 0.5 VCC)

R

R

MOUTL

LIN–

Figure 22. Analog Front-End Block Diagram (L-channel)

Table 2. Multiplexer Input Selection

CH2

CH1

CH0

CHANNEL

0

0

0

Mute

0

0

1

Channel 1 (default)

0

1

0

Channel 2

0

1

1

Channel 3

1

0

0

Channel 4

1

0

1

Channel 5

1

1

0

Channel 6

1

1

1

Mute