PCM1850 datasheet(4/34 Pages) TI2

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PCM1850

PCM1851

SLES108 − MARCH 2004

www.ti.com

Terminal Functions

PCM1851

TERMINAL

I/O

DESCRIPTIONS

NAME

I/O

DESCRIPTIONS

ADR

Mode control address select input (1)

AGND

—

Analog GND

BCK

I/O

Bit clock input/output(2)

DGND

—

Digital GND

DOUT

Audio data output

LRCK

I/O

Sampling clock input/output(2)

MOUTL

Multiplexer output, L-channel

MOUTR

Multiplexer output, R-channel

OVER

Overflow flag

RST

Reset, active LOW(1)

SCKI

System clock input; 256 fS, 384 fS, 512 fS or 768 fS(3)

SCL

Mode control clock input(3)

SDA

I/O

Mode control data input/output(4)

TEST0

Test 0, must be connected to GND (1)

TEST1

Test 1, must be connected to GND (1)

VCC

—

Analog power supply, 5-V

VDD

—

Digital power supply, 3.3-V

VINL1

Analog input 1, L-channel

VINL2

Analog input 2, L-channel

VINL3

Analog input 3, L-channel

VINL4

Analog input 4, L-channel

VINL5

Analog input 5, L-channel

VINL6

Analog input 6, L-channel

VINR1

Analog input 1, R-channel

VINR2

Analog input 2, R-channel

VINR3

Analog input 3, R-channel

VINR4

Analog input 4, R-channel

VINR5

Analog input 5, R-channel

VINR6

Analog input 6, R-channel

VREFS

—

Reference S decoupling capacitor (= 0.5 VCC)

VREF1

—

Reference 1 decoupling capacitor (= 0.5 VCC)

VREF2

—

Reference 2 decoupling capacitor (= VCC)

(1) Schmitt-trigger input with internal pulldown resistor (50 kΩ, typically), 5-V tolerant

(2) Schmitt-trigger input with internal pulldown resistor (50 kΩ, typically)

(3) Schmitt-trigger input, 5-V tolerant

(4) Schmitt-trigger input/open-drain LOW output, 5-V tolerant

PCM1850 Datasheet(PDF) 4 Page - Texas Instruments

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