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PCM1850 Datasheet(PDF) 21 Page - Texas Instruments |
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PCM1850 Datasheet(HTML) 21 Page - Texas Instruments |
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21 / 34 page ![]() PCM1850 PCM1851 SLES108 − MARCH 2004 www.ti.com 21 SYNCHRONIZATION WITH DIGITAL AUDIO SYSTEM In slave mode, the PCM1850/1851 operates under LRCK, synchronized with system clock SCKI. The PCM1850/1851 does not need a specific phase relationship between LRCK and SCKI, but does require the synchronization of LRCK and SCKI. If the relationship between LRCK and SCKI changes more than ±6 BCKs for 64 BCKs/frame (±5 BCKs for 48 BCKs/frame) during one sample period due to LRCK or SCKI jitter, internal operation of the ADC halts within 1/fS and digital output is forced into the BPZ code until resynchronization between LRCK and SCKI is completed. In the case of changes less than ±5 BCKs for 64 BCKs/frame (±4BCKs for 48BCK/frame), resynchronization with simultaneous discontinuity in the digital output does not occur. Figure 26 illustrates the digital output response for loss of synchronization and resynchronization. During undefined data, the PCM1850/1851 might generate some noise in the audio signal. Also, the transition of normal to undefined data and undefined or zero data to normal creates a discontinuity of data in the digital output, which could generate some noise in the audio signal. It is recommended to set RST (pin 10) to LOW to get stable analog performance when the sampling rate, interface mode, or data format is changed. 1/fS 32/fS NORMAL DATA ZERO DATA UNDEFINED DATA NORMAL DATA SYNCHRONOUS ASYNCHRONOUS SYNCHRONOUS Resynchronization Synchronization Lost DOUT State of Synchronization Figure 26. ADC Digital Output for Loss of Synchronization and Resynchronization Power-Down Control RST(pin 10) controls the entire ADC operation. During reset mode, the supply current of the analog section is shut off and the digital section is initialized. DOUT (pin 3) is also disabled. Halting SCKI, BCK, and LRCK is recommended to minimize power dissipation. RST POWER-DOWN MODE LOW Reset and power-down modes HIGH Normal operation mode Overflow Flag Output The PCM1850/1851 has an output flag (pin 4) that indicates when overflow occurs in the L-channel or R-channel, and this flag remains HIGH at least during the 8192/fS time for a momentary overflow occurrence. |
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