PCM4201

SBAS342B − DECEMBER 2004 − REVISED APRIL 2006

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12

Normal Speed, High Performance mode provides the best

overall dynamic performance at the expense of increased

power dissipation. Sampling rates up to 54kHz are

supported. The modulator oversampling rate is 128fS for

this mode, improving the overall dynamic range and

THD+N when compared to Low Power mode.

Double Speed mode supports sampling frequencies up to

108kHz with power dissipation that is somewhat higher

than Normal Speed, High Performance mode. The

modulator oversampling rate is 64fS for this mode.

The sampling mode is selected using the RATE input (pin

5). The RATE pin is a tri-level logic input, with the ability to

detect low, high, and floating (or high-impedance) states.

Table 3

shows

the

available

sampling

mode

configurations using the RATE pin. For the floating or

high-impedance case, it is best to drive the RATE pin with

a tri-state buffer, such as the Texas Instruments

SN74LVC1G125 or equivalent. This allows the buffer to be

disabled, setting the output to a high-impedance state.

Table 3. Sampling Mode Configuration

RATE (PIN 5)

SAMPLING MODE SELECTION

0

Double Speed

1

Normal Speed, Low Power

Float or Hi Z

Normal Speed, High Performance

AUDIO SERIAL PORT

The PCM4201 audio serial port is a 3-wire synchronous

serial interface comprised of the audio serial data output,

DATA (pin 9); a frame synchronization clock, FSYNC (pin

10); and a bit or data clock, BCK (pin 11). The FSYNC and

BCK clocks may be either inputs or outputs, supporting

either Slave or Master mode interfaces, respectively. The

audio data format is 24-bit linear PCM, represented as

two’s complement binary data with the MSB being the first

data bit in the frame. Figure 3 illustrates the audio frame

format, while Figure 4 and the Electrical Characteristics

table highlight the important timing parameters for the

audio serial port interface.

Data (4)

(1)(2)

1/f

S

Data (4)

FSYNC (3)

DATA

FSYNC (5)

DATA

Slave Mode

Frame Format

One Frame

Master Mode

Frame Format

NOTES: (1) One Frame = 128 BCK clock cycles for Normal Speed modes and 64 BCK clock cycles for Double Speed mode.

(2) If BCK = 128f

S when Normal Speed, Low Power sampling is enabled, then the frame will begin on the falling edge of the FSYNC clock input.

The FSYNC clockisinverted for this case.

(3) For Slave Mode operation, the FSYNC pulse width high period must be at least one BCK clock cycle in length, while the FSYNC pulse low

period must be at least one BCK clock cycle in length. Best performance is achieved when the FSYNC duty cycle is 50%.

(4) The audio data word length is 24 bits and is Left−Justified in the frame. The audio data is always presented in two’s complement binary format

with theMSB beingthe first databit in the frame.

(5) For Master mode operation, the FSYNC clock duty cycle is equal to 50%.

Figure 3. Audio Serial-Port Frame Format

t

DLK

t

DBK

t

H

t

BCKL

t

S

t

BCKH

FSYNC

BCK

DATA

Figure 4. Audio Serial-Port Timing