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VS6724 Datasheet(PDF) 107 Page - STMicroelectronics |
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VS6724 Datasheet(HTML) 107 Page - STMicroelectronics |
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107 / 118 page ![]() VS6724 Electrical characteristics 107/118 6.4 External clock The VS6724 requires an external clock. This clock is a CMOS digital input. The clock input is fail-safe in power down mode. 6.5 Chip enable CE is a CMOS digital input. The module is powered down when a logic 0 is applied to CE. See Section Figure 11.: Power up sequence for further information. Table 59. External clock CLK Range Unit Min. Typ. Max. DC coupled square wave VDD V Clock frequency(1) 1. The uwExternalClockFrequencyDenumerator and bExternalClockFrequencyDenominator registers must be configured to match the frequency supplied on the CLK pin. 6.50 27 MHz |
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