SY75608/612

DS20006363D-page 20

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4.0

FUNCTIONAL DESCRIPTION

The SY75608 and SY75612, respectively, are 2-to-8 and 2-to-12 PCIe clock buffers with ultra-low additive jitter. They

can be used in all PCIe 1/2/3/4/5/6 common clock and SRIS applications.

Each output can be enabled/disabled glitch-free via dedicated OE pins or via I2C bus.

The SY75608/612 each have an embedded low-dropout regulator (LDO) for superior power noise supply rejection. They

support 1.8V, 2.5V, and 3.3V supplies with tolerance of ±10%, which exceeds the ±9% required by PCIe Card Electro

Mechanical Specification.

Besides operating as fanout buffers, these devices can work as fixed frequency clock generators with external crystal.

Supported crystal frequencies are 8 MHz to 160 MHz.

4.1

Clock Input

The following figures show how to terminate input of the device in most common cases: Low Power HCSL (LPHCSL),

HCSL, and single-ended LVCMOS.

FIGURE 4-1:

Input Driven by LPHCSL Driver.

FIGURE 4-2:

Input Driven by HCSL Driver.

Figure 4-3 shows how to terminate a single-ended output, such as LVCMOS. This example assumes 50Ω transmission

line, which is the most common for single-ended CMOS signaling. Ideally, resistors R1 and R2 should be 100Ω each

and RO + RS should be 50Ω so that the transmission line is terminated at both ends with characteristic impedance. If

the driving strength of the output driver is not sufficient to drive low impedance, the value of series resistor RS should

be increased. This will reduce the voltage swing at the input, but this should be fine as long as the input voltage swing

requirement is not violated (Figure 1-3). The source resistors of RS = 270Ω could be used for a standard LVCMOS

driver. This will provide 516 mV of voltage swing for 3.3V LVCMOS driver with load current of (3.3V/2) * (1/(270Ω + 50Ω))

= 5.16 mA.

For optimum performance both differential input pins (_p and _n) need to be DC-biased to the same voltage. Hence,

the ratio R1/R2 should be equal to the ratio R3/R4.

Z0

Z0

MCHP

Device

Rs

VDD

VDD

Push-Pull Di eren al Driver (LPHCSL)

Rs

Z0

Z0

MCHP

Device

5

5

3

3

VDD

HCSL

Output