SY75608 datasheet(9/44 Pages) MICROCHIP

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DS20006363D-page 9

SY75608/612

Device-to-Device Output

Skew

tDOOSK

—

0.6

—

Input-to-Output Delay

tIOD

1.4

—

Output Enable Time

tEN

—

cycles Note 12

Output Disable Time

tDIS

—

cycles Note 12

Note 1: Measurement taken from differential waveform.

2: Measured from –150 mV to +150 mV on the differential waveform (derived from OUTx_p to OUTx_n). The

signal must be monotonic through the measurement region for rise and fall time. The 300 mV measure-

ment window is centered on the differential zero crossing. See Figure 1-5.

3: Measurement taken from single ended waveform.

4: Measured at crossing point where the instantaneous voltage value of the rising edge of OUTx_p equals

the falling edge of OUTx_n. See Figure 1-1.

5: Refers to the total variation from the lowest crossing point to the highest, regardless of which edge is

crossing. Refers to all crossing points for this measurement. See Figure 1-1.

6: Defined as the total variation of all crossing voltages of Rising OUTx_p and Falling OUTx_n. This is the

maximum allowed variance in VCROSS for any particular system. See Figure 1-2.

7: tSTABLE is the time the differential clock must maintain a minimum ±150 mV differential voltage after ris-

ing/falling edges before it is allowed to droop back into the VRB ±100 mV differential range. See

Figure 1-6.

8: Defined as the maximum instantaneous voltage including overshoot. See Figure 1-1.

9: Defined as the minimum instantaneous voltage including undershoot. See Figure 1-1.

10: Matching applies to rising edge rate for OUTx_p and falling edge rate for OUTx_n. It is measured using a

±75 mV window centered on the median cross point where OUTx_p rising meets OUTx_n falling. The

median cross point is used to calculate the voltage thresholds the oscilloscope is to use for the edge rate

calculations. The Rise Edge Rate of OUTx_p should be compared to the Fall Edge Rate of OUTx_n; the

maximum allowed difference should not exceed 20% of the slowest edge rate. See Figure 1-3.

11: System board compliance measurements must use the test load card described in Figure 1-7. OUTx_p

and OUTx_n are to be measured at the load capacitors CLOAD. Single-ended probes must be used for

measurements requiring single-ended measurements. Either single-ended probes with math or differential

probe can be used for differential measurements. Test load CLOAD = 2 pF.

12: Output Enable control (pin or register) is synchronous with the input clock and it takes four rising edges

before output gets enabled or disabled. Hence the minimum input frequency is greater than 0 Hz. Once

the outputs are enabled the input clock frequency can be reduced to 0 Hz.

JITTER AND PHASE NOISE

Parameters

Symbol

Min.

Typ.

Max.

Units

Conditions

Peak-to-Peak Additive

Jitter

AJRMS_PP

—

5.1

Note 1, Note 2

Additive Jitter per PCIe

1.0 (1.5 MHz to 22 MHz)

tjPCIe_1.0

—

0.7

0.9

psRMS Note 1, Note 2

Additive Jitter per PCIe

2.0 High Band (1.5 MHz

to 50 MHz)

tjPCIe_2.0_high

—

100

fsRMS Note 1, Note 2

Additive Jitter per PCIe

2.0 Low Band (10 kHz to

1.5 MHz)

tjPCIe_2.0_low

—

fsRMS Note 1, Note 2

Additive Jitter per PCIe

2.0 Mid Band (5 MHz to

16 MHz)

tjPCIe_2.0_mid

—

fsRMS Note 1, Note 2

OUTPUT ELECTRICAL CHARACTERISTICS (CONTINUED)

Electrical Characteristics: VDD = 3.3V ±10%, VDD = 2.5V ±10%, VDD = 1.8V ±10%, TA = –40°C to +105°C, unless

noted. CLOAD = 2 pF.

Parameters

Symbol

Min.

Typ.

Max.

Units

Conditions

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