Digital Interface

SDA

SCL

Slave Address

Repeated If More Bytes Are Transferred

R/W

Direction

Bit

Acknowledgement

Signal from

Receiver

Acknowledgement

Signal from

Receiver

Start

Condition

1

2

7

6

8

9

1

2

3-7

8

9

ACK

ACK

Stop Condition

or Repeated

Start Condition

TSC2003-Q1

SBAS454 – DECEMBER 2008 ........................................................................................................................................................................................... www.ti.com

The TSC2003 supports the I2C serial bus and data transmission protocol in all three defined modes: standard,

fast, and high-speed. A device that sends data onto the bus is defined as a transmitter, and a device receiving

data as a receiver. The device that controls the message is called a master. The devices that are controlled by

the master are slaves. The bus must be controlled by a master device which generates the serial clock (SCL),

controls the bus access, and generates the Start and Stop conditions. The TSC2003 operates as a slave on the

I2C bus. Connections to the bus are made via the open-drain I/O lines SDA and SDL.

The following bus protocol has been defined, as shown in Figure 11:

• Data transfer may be initiated only when the bus is not busy.

• During data transfer, the data line must remain stable whenever the clock line is high. Changes in the data

line while the clock line is high are interpreted as control signals.

Figure 11. I2C Bus Protocol

Accordingly, the following bus conditions have been defined:

Bus Not Busy: Both data and clock lines remain high.

Start Data Transfer: A change in the state of the data line, from high to low, while the clock is high defines a

Start condition.

Stop Data Transfer: A change in the state of the data line, from low to high, while the clock line is high defines a

Stop condition.

Data Valid: The state of the data line represents valid data when, after a Start condition, the data line is stable

for the duration of the high period of the clock signal. There is one clock pulse per bit of data.

Each data transfer is initiated with a Start condition and terminated with a Stop condition. The number of data

bytes transferred between Start and Stop conditions is not limited, and is determined by the master device. The

information is transferred byte-wise, and each receiver acknowledges with a ninth-bit.

Within the I2C bus specifications, a standard mode (100-kHz clock rate), a fast mode (400-kHz clock rate), and a

high-speed mode (3.4-MHz clock rate) are defined. The TSC2003 works in all three modes.

Acknowledge: Each receiving device, when accessed, is obliged to generate an acknowledge after the

reception of each byte. The master device must generate an extra clock pulse, which is associated with this

acknowledge bit.

A device that acknowledges must pull down the SDA line during the acknowledge clock pulse in such a way that

the SDA line is stable low during the high period of the acknowledge clock pulse. Of course, setup and hold

times must be taken into account. A master must signal an end of data to the slave by not generating an

acknowledge bit on the last byte that has been clocked out of the slave. In this case, the slave must leave the

data line high to enable the master to generate the Stop condition.

18

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Product Folder Link(s): TSC2003-Q1