TSC2003-Q1

SBAS454 – DECEMBER 2008 ........................................................................................................................................................................................... www.ti.com

TIMING CHARACTERISTICS (continued)

TA = –40°C to 85°C, VDD = 2.7 V (unless otherwise noted) (see Figure 1)

PARAMETER

TEST CONDITIONS

MIN

MAX

UNIT

Standard mode

250

tSU; DAT

Data setup time

Fast mode

100

ns

High-speed mode

10

Standard mode

0

3.45

µs

Fast mode

0

0.9

tHD; DAT

Data hold time

High-speed mode, Cb = 100 pF max

0

70

ns

High-speed mode, Cb = 400 pF max

0

150

Standard mode

1000

Fast mode

20 + 0.1Cb

300

trCL

Rise time of SCL signal

ns

High-speed mode, Cb = 100 pF max

10

80

High-speed mode, Cb = 400 pF max

20

160

Standard mode

1000

Fast mode

20 + 0.1Cb

300

Rise time of SCL signal after a repeated Start

trCL1

ns

condition and after an acknowledge bit

High-speed mode, Cb = 100 pF max

10

80

High-speed mode, Cb = 400 pF max

20

160

Standard mode

300

Fast mode

20 + 0.1Cb

300

tfCL

Fall time of SCL signal

ns

High-speed mode, Cb = 100 pF max

10

80

High-speed mode, Cb = 400 pF max

20

160

Standard mode

1000

Fast mode

20 + 0.1Cb

300

trDA

Rise time of SDA signal

ns

High-speed mode, Cb = 100 pF max

10

80

High-speed mode, Cb = 400 pF max

20

160

Standard mode

300

Fast mode

20 + 0.1Cb

300

tfDA

Fall time of SDA signal

ns

High-speed mode, Cb = 100 pF max

10

80

High-speed mode, Cb = 400 pF max

20

160

Standard mode

4

µs

tSU; STO

Setup time for Stop condition

Fast mode

600

ns

High-speed mode

160

Standard mode

400

Fast mode

400

Cb

Capacitive load for SDA or SCL

pF

High-speed mode, SCL = 1.7 MHz

400

High-speed mode, SCL = 3..4 MHz

100

Fast mode

0

50

tSP

Pulse width of spike suppressed

ns

High-speed mode

0

10

Standard mode

Noise margin at the high level for each

VnH

Fast mode

0.2 × VDD

V

connected device (including hysteresis)

High-speed mode

Standard mode

Noise margin at the low level for each

VnL

Fast mode

0.1 × VDD

V

connected device (including hysteresis)

High-speed mode

6

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