Address Byte

1

0

0

1

0

A1

A0

R/W

MSB

LSB

Command Byte

C3

C2

C1

C0

PD1

PD0

M

X

MSB

LSB

TSC2003-Q1

www.ti.com ........................................................................................................................................................................................... SBAS454 – DECEMBER 2008

Figure 11 details how data transfer is accomplished on the I2C bus. Depending upon the state of the R/W bit, two

types of data transfer are possible:

• Data transfer from a master transmitter to a slave receiver. The first byte transmitted by the master is the

slave address. Next follows a number of data bytes. The slave returns an acknowledge bit after the slave

address and each received byte.

• Data transfer from a slave transmitter to a master receiver. The first byte (the slave address) is transmitted by

the master. The slave then returns an acknowledge bit. Next, a number of data bytes are transmitted by the

slave to the master. The master returns an acknowledge bit after all received bytes other than the last one. At

the end of the last received byte, a ‘not acknowledge’ is returned.

The master device generates all of the serial clock pulses and the Start and Stop conditions. A transfer is ended

with a Stop condition or a repeated Start condition. Because a repeated Start condition is also the beginning of

the next serial transfer, the bus is not released.

The TSC2003 may operate in the following two modes:

• Slave receiver mode: Serial data and clock are received through SDA and SCL. After each byte is received,

an acknowledge bit is transmitted. Start and Stop conditions are recognized as the beginning and end of a

serial transfer. Address recognition is performed by hardware after reception of the slave address and

direction bit.

• Slave transmitter mode: The first byte (the slave address) is received and handled as in the slave receiver

mode. However, in this mode the direction bit indicates that the transfer direction is reversed. Serial data is

transmitted on SDA by the TSC2003 while the serial clock is input on SCL. Start and Stop conditions are

recognized as the beginning and end of a serial transfer.

The address byte, as shown in Figure 12, is the first byte received following the Start condition from the master

device. The first five bits (MSBs) of the slave address are factory preset to 10010. The next two bits of the

address byte are the device select bits: A1 and A0. Input pins (A1 and A0) on the TSC2003 determine these two

bits of the device address for a particular TSC2003. Therefore, a maximum of four devices with the same preset

code can be connected on the same bus at one time.

Figure 12. Address Byte

The A1–A0 address inputs can be connected to VDD or digital ground. The last bit of the address byte (R/W)

defines the operation to be performed. When set to a "1", a read operation is selected; when set to a "0", a write

operation is selected. Following the Start condition, the TSC2003 monitors the SDA bus and checks the device

type identifier being transmitted. Upon receiving the 10010 code, the appropriate device select bits, and the R/W

bit, the slave device outputs an acknowledge signal on the SDA line.

The TSC2003 operating mode is determined by a command byte, which is shown in Figure 13.

Figure 13. Command Byte

The bits in the device command byte are defined as follows:

• C3–C0: Configuration bits. These bits set the input multiplexer address and functions that the TSC2003 will

perform, as shown in Table 1.

• PD1–PD0: Power-down bits. These two bits select the power-down mode that the TSC2003 will enter after

the current command completes, as shown in Table 2.

Copyright © 2008, Texas Instruments Incorporated

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Product Folder Link(s): TSC2003-Q1