RT =

(1/F) - 172 x 10

-9

182 x 10

-12

LM5030

SNVS215D – APRIL 2003 – REVISED NOVEMBER 2015

www.ti.com

Feature Description (continued)

7.3.5 Oscillator, Shutdown and Sync Capability

The LM5030 oscillator is set by a single external resistor connected between the RT pin and return. To set a

desired oscillator frequency, the necessary RT resistor can be calculated in Equation 1:

(1)

Each output switches at half the oscillator frequency in a push-pull configuration. The LM5030 can also be

synchronized to an external clock. The external clock must be of higher frequency than the free running

frequency set by the RT resistor. The clock signal should be capacitively coupled into the RT pin with a 100-pF

capacitor. A peak voltage level greater than 3 V with respect to ground is required for detection of the sync pulse.

The sync pulse width should be set in the 15- to 150-ns range by the external components. The RT resistor is

always required, whether the oscillator is free running or externally synchronized. The voltage at the RT pin is

internally regulated to a nominal 2 V.

Locate the RT resistor close to the device and connected directly to the pins of the IC (RT and GND).

7.3.6 Slope Compensation

The PWM comparator compares the current sense signal to the voltage derived from the COMP pin. The COMP

voltage is set by either the internal error amplifier or an external error amplifier through an optocoupler. At duty

cycles greater than 50% (composite of alternating outputs) current mode control circuits are prone to

subharmonic oscillation. By adding an additional ramp signal to the current sense ramp signal this condition can

be avoided. The LM5030 integrates this slope compensation by buffering the internal oscillator ramp and

summing it internally to the current sense (CS) signal. Additional slope compensation may be added by

increasing the source impedance of the current sense signal.

7.3.7 Soft Start and Shutdown

The soft-start feature allows the converter to gradually reach the initial steady state operating point, thus reducing

start-up stresses and surges. An internal 10-

μA current source and an external capacitor generate a ramping

voltage signal that limits the error amplifier output during start-up. In the event of a second level current limit fault,

the soft-start capacitor will be fully discharged which disables the output drivers. When the fault condition is no

longer present, the soft-start capacitor is released to ramp and gradually restart the converter. The SS pin can

also be used to disable the controller. If the SS pin voltage is pulled down below 0.45 V (nominal) the controller

will disable the outputs and enter a low power state.

7.3.8 OUT1, OUT2, and Time Delay

The LM5030 provides two alternating outputs, OUT1 and OUT2. The internal gate drivers can each sink 1.5-A

peak each. The maximum duty cycle for each output is inherently limited to less than 50%. The typical deadtime

between the falling edge of one gate driver output and the rising edge of the other gate driver output is 135 ns.

7.3.9 Thermal Protection

Internal thermal-shutdown circuitry is provided to protect the integrated circuit in the event the excessive junction

temperature. When activated, typically at 165°C, the controller is forced into a low-power reset state, disabling

the output drivers and the bias regulator. This feature is provided to prevent catastrophic failures from accidental

device overheating.

12

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