LP5523 datasheet(34/61 Pages) TI2

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LP5523

SNVS550E – SEPTEMBER 2009 – REVISED JANUARY 2017

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3A STATUS/INTERRUPT

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3A — Bit [7] LEDTEST_MEAS_DONE

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This bit indicates when the LED test is done, and the result is written to the LED TEST ADC register.

Typically the conversion takes 2.7 milliseconds to complete.

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1 = LED test done.

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0 = LED test not done.

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This bit is a read-only bit, and it is cleared (to 0) automatically after a read operation.

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3A — Bit [6] MASK_BUSY

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Mask bit for interrupts generated by STARTUP_BUSY or ENGINE_BUSY.

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1 = Interrupt events are masked; that is, no external interrupt is generated from STARTUP_BUSY or

ENGINE_BUSY event (default).

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0 = External interrupt are generated when STARTUP_BUSY or ENGINE_BUSY condition is no longer

true. Reading the register 3A clears the status bits [5:4] and releases INT pin to high state.

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3A — Bit [5] STARTUP_BUSY

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A status bit which indicates that the device is running the internal start-up sequence. See Modes Of

Operation for details.

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1 = internal start-up sequence running Note: STARTUP_BUSY = 1 always when CHIP_EN bit is 0.

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0 = internal start-up sequence completed

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3A — Bit [4] ENGINE_BUSY

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A status bit which indicates that a program execution engine is clearing internal registers. Serial bus

master should not write or read program memory, or registers 00H, 37H to 39H or 4CH to 4EH, when this

bit is set to 1.

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1 = at least one of the engines is clearing internal registers

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0 = engine ready

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3A — Bit [3] EXT_CLK_USED

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1 = external clock detected

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0 = external clock not detected

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This bit is high when external clock signal on CLK pin is detected. CLK_DET_EN bit high in address 36

enables the clock detection.

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3A — Bits [2:0] ENG1_INT, ENG2_INT, ENG3_INT

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1 = interrupt set.

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0 = interrupt unset/cleared.

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Interrupt bits for program execution engine 1, 2 and 3, respectively. These bits are set by END or INT

instruction. Reading the interrupt bit clears the interrupt.

3B GPO

The LP5523 has one general purpose output pin (GPO). The status of the pin can be controlled with this register.

Also, INT pin can be configured to function as a GPO by setting the bit INT_CONF. When INT is configured to

function as a GPO, output level is defined by the VDD voltage.

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3B — Bit [2] INT_CONF

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0 = INT pin is set to function as an interrupt pin (default).

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1 = INT pin is configured to function as a GPO.

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3B — Bit [1] GPO

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0 = GPO pin state is low.

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1 = GPO pin state is high.

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GPO pin is a digital CMOS output, and no pulldown resistor is needed.

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3B — Bit [0] INT_GPO

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0 = INT pin state is low (if INT_CONF = 1).

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1 = INT pin state is high (if INT_CONF = 1).

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When the GPO function of the INT pin is disabled, it operates as an open drain pin. INT signal is active

low; that is, when an interrupt signal is sent, the pin is pulled to GND. External pullup resistor is needed

for proper functionality.

LP5523 Datasheet(PDF) 34 Page - Texas Instruments

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