PCM1789 datasheet(24/42 Pages) TI2

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BUF

D-SU

D-HD

SDA-R

SDA-F

P-SU

SCL-F

S-HD

LOW

SCL-R

S-SU

S-HD

START

Repeated

START

STOP

SDA

SCL

PCM1789-Q1

SBAS546

– MARCH 2011

www.ti.com

TIMING REQUIREMENTS: SCL AND SDA

A detailed timing diagram for SCL and SDA is shown in Figure 36.

Figure 36. SCL and SDA Control Interface Timing

Table 12. Timing Requirements for Figure 36

STANDARD MODE

FAST MODE

SYMBOL

PARAMETER

MIN

MAX

MIN

MAX

UNIT

fSCL

SCL clock frequency

100

400

kHz

tBUF

Bus free time between STOP and START condition

4.7

1.3

μs

tLOW

Low period of the SCL clock

4.7

1.3

μs

tHI

High period of the SCL clock

4.0

0.6

μs

tS-SU

Setup time for START/Repeated START condition

4.7

0.6

μs

tS-HD

Hold time for START/Repeated START condition

4.0

0.6

μs

tD-SU

Data setup time

250

100

tD-HD

Data hold time

3450

900

tSCL-R

Rise time of SCL signal

1000

20 + 0.1 CB

300

tSCL-F

Fall time of SCL signal

1000

20 + 0.1 CB

300

tSDA-R

Rise time of SDA signal

1000

20 + 0.1 CB

300

tSDA-F

Fall time of SDA signal

1000

20 + 0.1 CB

300

tP-SU

Setup time for STOP condition

4.0

0.6

μs

tGW

Allowable glitch width

N/A

Capacitive load for SDA and SCL line

400

100

Noise margin at high level for each connected device

VNH

0.2

× VDD

0.2

× VDD

(including hysteresis)

Noise margin at low level for each connected device

VNL

0.1

× VDD

0.1

× VDD

(including hysteresis)

VHYS

Hysteresis of Schmitt trigger input

N/A

0.05

× VDD

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