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TDP142

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SLLSEZ1C – SEPTEMBER 2017 – REVISED MAY 2019

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8.5 Programming

For further programmability, the TDP142 can be controlled using I2C. When I2C_EN !=0, the SCL and SDA pins

are used for I2C clock and I2C data respectively.

Table 4. TDP142 I2C Target Address

DPEQ0/A1

PIN LEVEL

A0

PIN LEVEL

Bit 7 (MSB)

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0 (W/R)

0

0

1

0

0

0

1

0

0

0/1

0

R

1

0

0

0

1

0

1

0/1

0

F

1

0

0

0

1

1

0

0/1

0

1

1

0

0

0

1

1

1

0/1

R

0

0

1

0

0

0

0

0

0/1

R

R

0

1

0

0

0

0

1

0/1

R

F

0

1

0

0

0

1

0

0/1

R

1

0

1

0

0

0

1

1

0/1

F

0

0

0

1

0

0

0

0

0/1

F

R

0

0

1

0

0

0

1

0/1

F

F

0

0

1

0

0

1

0

0/1

F

1

0

0

1

0

0

1

1

0/1

1

0

0

0

0

1

1

0

0

0/1

1

R

0

0

0

1

1

0

1

0/1

1

F

0

0

0

1

1

1

0

0/1

1

1

0

0

0

1

1

1

1

0/1

The following procedure should be followed to write to TDP142 I2C registers:

1. The master initiates a write operation by generating a start condition (S), followed by the TDP142 7-bit

address and a zero-value “W/R” bit to indicate a write cycle.

2. The TDP142 acknowledges the address cycle.

3. The master presents the sub-address (I2C register within TDP142) to be written, consisting of one byte of

data, MSB-first.

4. The TDP142 acknowledges the sub-address cycle.

5. The master presents the first byte of data to be written to the I2C register.

6. The TDP142 acknowledges the byte transfer.

7. The master may continue presenting additional bytes of data to be written, with each byte transfer completing

with an acknowledge from the TDP142.

8. The master terminates the write operation by generating a stop condition (P).

The following procedure should be followed to read the TDP142 I2C registers:

1. The master initiates a read operation by generating a start condition (S), followed by the TDP142 7-bit

address and a one-value “W/R” bit to indicate a read cycle.

2. The TDP142 acknowledges the address cycle.

3. The TDP142 transmit the contents of the memory registers MSB-first starting at register 00h or last read sub-

address+1. If a write to the T I2C register occurred prior to the read, then the TDP142 shall start at the sub-

address specified in the write.

4. The TDP142 shall wait for either an acknowledge (ACK) or a not-acknowledge (NACK) from the master after

each byte transfer; the I2C master acknowledges reception of each data byte transfer.

5. If an ACK is received, the TDP142 transmits the next byte of data.

6. The master terminates the read operation by generating a stop condition (P).