INDP3P

18

INDP3N

19

TEST2/SDA

22

DPEN/HPDIN

23

RSVD4

7

VCC

6

RSVD1

3

DPEQ1

2

INDP0N

10

OUTDP3N

31

AUXN

25

INDP2N

16

INDP2P

15

INDP1P

12

SNOOPENZ/RSVD8

29

VCC

28

INDP0P

9

HPDIN/RSVD9

32

RSVD6

26

INDP1N

13

OUTDP2N

34

RSVD10

35

OUTDP1N

36

OUTDP1P

37

RSVD11

38

OUTDP0N

39

OUTDP0P

40

TPAD

41

RSVD7

27

OUTDP3P

30

DPEQ0/A1

14

A0

11

VCC

20

TEST1/SCL

21

AUXP

24

I2C_EN

17

VCC

1

OUTDP2P

33

RSVD5

8

RSVD2

4

RSVD3

5

U1

TDP142RNQ

0.1uF

C6

0.1uF

C7

0.1uF

C8

0.1uF

C9

0.1uF

C10

0.1uF

C11

0.1uF

C12

0.1uF

C23

0.1uF

C13

0.1uF

C14

0.1uF

C15

0.1uF

C16

0.1uF

C17

0.1uF

C18

0.1uF

C19

0.1uF

C20

10k

R5

10k

R6

GND

OUTDP0P

OUTDP0N

OUTDP1P

OUTDP1N

OUTDP2P

OUTDP2N

OUTDP3P

OUTDP3N

OUTDP1P

OUTDP1N

OUTDP0P

OUTDP0N

OUTDP3P

OUTDP3N

OUTDP2P

OUTDP2N

GND

2

1

4

U2

SN74AHC1G125DBVR

GND

3V3P

SNOOPENZ

SNOOPENZ

HPDIN

DPEQ1

DPEQ2

A0

GPU with Dual mode support

ML0_P

ML0_N

ML1_P

ML1_N

ML2_P

ML2_N

ML3_P

ML3_N

AUX_P

AUX_N

SDA

SCL

CAD

HPD

100k

R1

100k

R2

0.1uF

C21

0.1uF

C22

3P3V

GND

AUX_N

AUX_P

AUX_P

AUX_N

ML1_P

4

ML1_N

6

ML0_P

1

ML0_N

3

ML3_P

10

ML3_N

12

ML2_P

7

ML2_N

9

DP_PWR

20

AUX_P

15

AUX_N

17

HPD

18

CONFIG1

13

GND

2

GND

5

GND

8

GND

11

CONFIG2

14

GND

16

GND

21

GND

22

GND

23

GND

24

RTN

19

DisplayPort Receptacle

HPDIN

AUX_P

AUX_N

3.3V

CAD

1M

R9

GND

5M

R10

CAD

CAD

HPDIN

I2C_EN

1k

R11

1k

R12

1k

R13

1k

R15

1k

R16

GND

GND

GND

3P3V

3P3V

I2C_EN

DPEQ0

DPEQ1

20k

R14

20k

R17

10uF

C1

0.1uF

C2

0.1uF

C3

0.1uF

C4

0.1uF

C5

3P3V

3V3P

Board_3P3V

220 ohm

FB

3P3V

2k

R3

2k

R4

DDC_EN

DDC_EN

DDC_EN

1k

R7

10k

R8

AUX_N

AUX_P

3V3P

Copyright © 2017, Texas Instruments Incorporated

22

TDP142

SLLSEZ1C – SEPTEMBER 2017 – REVISED MAY 2019

www.ti.com

Product Folder Links: TDP142

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Copyright © 2017–2019, Texas Instruments Incorporated

9.2 Typical Application

9.2.1 Source Application Implementation

Figure 18 shows the schematic for the Source side application. The TDP142 is placed between the DisplayPort

Graphics Processor Unit (GPU) and the DisplayPort receptacle. The TDP142 monitors AUX traffic for power

management purposes when SNOOPENZ is low.

Figure 18. The Block Diagram of DisplayPort Source Application

9.2.1.1 Design Requirement

The TDP142 can be designed into many types of applications. All applications have certain requirements for the

system to work properly. For example, source application uses different hardware configuration on the HPD

channel and AUX channel from a sink application. The device can be configured by using I2C. However, the

GPIO configuration is provided as I2C is not available in all cases. Additionally, because sources may have

different naming conventions, please confirm the link between source and receptacle is correctly mapped through

the TDP142.

Table 11. Design Parameters

PARAMETER

VALUE

Maximum Operating data rate

(RBR, HBR, HBR2, or HBR3)

HBR3 (8.1 Gbps)

Supply voltage

3.3V

Trace length/width of A

12 inch /6 mil width

Trace length/width of B

2 inch/ 6 mil width

Main link AC decoupling capacitor

(75 nF to 265 nF)

Recommend 100nF

Control mode (I2C or GPIO)

GPIO (I2C_EN = 0)

Dual Mode DisplayPort Support (Yes/No)

Yes. SNOOPENZ must be connected to CONFIG1 thru a buffer.