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Output Short Circuit Protection

Selecting the Short Circuit Current Limit Threshold

Synchronous Rectification and Gate Drive

TPS40040, TPS40041

SLUS700D – MARCH 2006 – REVISED DECEMBER 2007

To minimize circuit losses, the TPS40040/1 uses the RDS(on) of the upper MOSFET switch as the current sensing

element. The current limit comparator, initially blanked during the first portion of each switching cycle, senses the

voltage across the high-side MOSFET when it is fully ON. This voltage is compared to an internally selected

short circuit current (SCC) limit threshold voltage. If the comparator senses a voltage drop across the high-side

MOSFET greater than the SCC limit threshold, it outputs an OC pulse. This terminates the current PWM pulse

preventing further current ramp-up, and sets the fault counter to count up one count on the next clock cycle.

Similarly, if no OC pulse is detected, the fault counter decrements by one count. If seven OC pulses are

summed, a fault condition is declared and the upper switch of the PWM output of the chip is immediately

disabled (turned OFF) and remains that way until the fault time-out period has elapsed. Both HDRV and LDRV

drivers are kept OFF during the fault time-out.

The fault time-out period is determined by cycling through seven internal soft-start time periods. At the end of the

fault time-out period, startup is attempted again.

The main purpose is for hard fault protection of the power switches. The internal SCC voltage has a positive

temperature coefficient designed to improve the short circuit threshold tolerance variation with temperature.

However, given the tolerance of the voltage thresholds and the RDS(on) range for a MOSFET, it is possible to

apply a load that thermally damages the external MOSFETs.

The TPS40040/1 uses one of three user selectable voltage thresholds. During the calibration interval at power on

or enable (Figure 19), the TPS40040/1 monitors the current out of the COMP pin and selects a threshold based

on the sensed value. If the current is zero; that is, no resistor is connected between COMP and GND, then the

threshold voltage level is 180 mV. If a 2.4-k

Ω resistor is connected between COMP and GND, then the threshold

voltage level is 105 mV. If a 12-k

Ω resistor is connected between COMP and GND, then the threshold voltage is

310 mV.

Once calibration is complete, the selected SCP threshold level is latched into place and remains constant. In

addition, the sensing circuits on COMP pin during calibration are disconnected from the COMP pin, and soft start

is allowed to begin.

In a buck converter, when the upper switch MOSFET turns off, current is flowing in the inductor to the load. This

current cannot be stopped immediately without using infinite voltage. To give this current a path to flow and

maintain voltage levels at a safe level, a rectifier or catch device is used. This device can be either a diode, or it

can be a controlled active device. The TPS40040/1 provides a signal to drive an N-channel MOSFET as a

synchronous rectifier (SR). This control signal is carefully coordinated with the drive signal for the main switch so

that there is minimum dead time from the time that the SR turns OFF and the upper switch MOSFET turns ON,

and minimum delay from when the upper switch MOSFET turns OFF and the SR turns ON.

NOTE:

The longer the time spent in diode conduction during the rectifier conduction period,

the lower the converter efficiency.

The drivers for the external HDRV and LDRV MOSFETs are capable of driving a gate to source voltage of

approximately 5 V. At VDD = 5 V, the drivers are capable of driving MOSFETs appropriate for a 15-A converter.

The LDRV driver switches between VDD and ground, while HDRV driver is referenced to SW and switches

between BOOT and SW. The drivers have non-overlapping timing that is governed by an adaptive delay circuit

that minimizes body diode conduction in the synchronous rectifier.

Copyright © 2006–2007, Texas Instruments Incorporated

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Product Folder Link(s): TPS40040 TPS40041