TPS62650 datasheet(21/43 Pages) TI2

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TPS62650-Q1

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SLVSB62B – MARCH 2012 – REVISED FEBRUARY 2013

DETAILED DESCRIPTION

Operation

The TPS62650-Q1 is a synchronous step-down converter typically operates at a regulated 6-MHz frequency

pulse width modulation (PWM) at moderate to heavy load currents. At light load currents, the TPS62650-Q1

converter operates in power-save mode with pulse frequency modulation (PFM) and automatic transition into

PWM operation when the load current increases.

The TPS62650-Q1 integrates an I2C compatible interface allowing transfers up to 3.4 Mbps. This communication

interface can be used for dynamic voltage scaling with voltage steps down to 12.5 mV, for reprogramming the

mode of operation (PFM or forced PWM) or disable/enabling the output voltage for instance. For more details,

see the I2C interface and register description section.

The converter uses a unique frequency locked ring oscillating modulator to achieve best-in-class load and line

response and allows the use of tiny inductors and small ceramic input and output capacitors. At the beginning of

each switching cycle, the P-channel MOSFET switch is turned on and the inductor current ramps up rising the

output voltage until the main comparator trips, then the control logic turns off the switch.

One key advantage of the non-linear architecture is that there is no traditional feed-back loop. The loop response

to change in VO is essentially instantaneous, which explains its extraordinary transient response. The absence of

a traditional, high-gain compensated linear loop means that the TPS62650-Q1 is inherently stable over a range

of small L and CO.

Although this type of operation normally results in a switching frequency that varies with input voltage and load

current, an internal frequency lock loop (FLL) holds the switching frequency constant over a large range of

operating conditions.

Combined with best in class load and line transient response characteristics, the low quiescent current of the

device (ca. 38

μA) allows to maintain high efficiency at light load, while preserving fast transient response for

applications requiring tight output regulation.

SWITCHING FREQUENCY

The magnitude of the internal ramp, which is generated from the duty cycle, reduces for duty cycles either set of

50%. Thus, there is less overdrive on the main comparator inputs which tends to slow the conversion down. The

intrinsic maximum operating frequency of the converter is about 10MHz to 12MHz, which is controlled to circa.

6MHz by a frequency locked loop.

When high or low duty cycles are encountered, the loop runs out of range and the conversion frequency falls

below 6MHz. The tendency is for the converter to operate more towards a "constant inductor peak current" rather

than a "constant frequency". In addition to this behavior which is observed at high duty cycles, it is also noted at

low duty cycles.

When the converter is required to operate towards the 6MHz nominal at extreme duty cycles, the application can

be assisted by decreasing the ratio of inductance (L) to the output capacitor's equivalent serial inductance (ESL).

This increases the ESL step seen at the main comparator's feed-back input thus decreasing its propagation

delay, hence increasing the switching frequency.

POWER-SAVE MODE

If the load current decreases, the converter will enter Power Save Mode operation automatically. During power-

save mode the converter operates in discontinous current (DCM) single-pulse PFM mode, which produces low

output ripple compared with other PFM architectures.

When in power-save mode, the converter resumes its operation when the output voltage trips below the nominal

voltage. It ramps up the output voltage with a minimum of one pulse and goes into power-save mode when the

inductor current has returned to a zero steady state. The PFN on-time varies inversely proportional to the input

voltage and proportional to the output voltage giving the regulated switching frequency when is steady-state.

PFM mode is left and PWM operation is entered as the output current can no longer be supported in PFM mode.

As a consequence, the DC output voltage is typically positioned ca 0.5% above the nominal output voltage and

the transition between PFM and PWM is seamless.

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