TPS62650-Q1

SLVSB62B – MARCH 2012 – REVISED FEBRUARY 2013

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ELECTRICAL CHARACTERISTICS (continued)

Minimum and maximum values are at VI = 2.3V to 5.5V, VO = 1.2 V, EN = 1.8V, EN_DCDC bit = 1, AUTO mode and

TA = -40°C to 105°C; Circuit of Parameter Measurement Information section (unless otherwise noted). Typical values are at

VI = 3.6V, VO = 1.2 V, EN = 1.8V, EN_DCDC bit = 1, AUTO mode and TA = 25°C (unless otherwise noted).

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

OUTPUT

2.3 V

≤ VI ≤ 5.5 V, 0 mA ≤ IO(DC) ≤ 800 mA

VO = 0.75 V, 1.05 V, 1.20 V, 1.4375 V (TPS62650-Q1)

–4%

4%

PWM operation

TA= 85°C

Regulated DC output

2.3 V

≤ VI ≤ 5.5 V, 0 mA ≤ IO(DC) ≤ 800 mA

–2%

2%

voltage accuracy

VO = 0.75 V, 1.05 V, 1.20 V, 1.4375 V (TPS62650-Q1)

PWM operation

TPS62650-

VO

2.3 V

≤ VI ≤ 5.5 V, 0 mA ≤ IO(DC) ≤ 800 mA

Q1/1

VO = 0.75 V, 1.05 V, 1.20 V, 1.4375 V (TPS62650-Q1)

–4%

4%

PFM/PWM Operation

Regulated DC output

VI = 3.6 V, VO = 1.20 V, IO(DC) = 50 mA

-0.5%

+0.5%

voltage temperature drift

-40°C

≤ TA ≤ 105°C. PWM operation

Line regulation

VI = VO + 0.5 V (min 2.3 V) to 5.5 V, IO(DC) = 200 mA

0.13

%/V

Load regulation

IO(DC) = 0 mA to 800 mA

–0.00046

%/mA

Feedback input resistance

480

k

Ω

VO = 1.05 V, VSEL = GND, IO(DC) = 1 mA

16

mVPP

PFM operation

ΔVO

Power-save mode ripple voltage

VO = 1.20 V, VSEL = VI, IO(DC) = 1 mA

16

mVPP

PFM operation

DAC

TPS62650-

Resolution

6

Bits

Q1

Differential nonlinearity

Specified monotonic by design

±0.4

LSB

TIMING

Setup Time Between

TPS62650-

Rising EN and Start of

50

μs

Q1/1

I2C Stream

Output voltage settling

TPS62650-

From min to max output voltage,

VO

12

μs

time

Q1/1

IO(DC) = 500 mA, VSEL = VI, PWM operation

Time from active EN to VO

125

VO = 1.2 V, IO = 0 mA, PWM operation

TPS62650-

Start-up time

μs

Q1/1

Time from active EN to VO

120

VO = 1.05 V, IO = 0 mA, PFM operation

I

2C INTERFACE TIMING CHARACTERISTICS(1)

PARAMETER

TEST CONDITIONS

MIN

MAX

UNIT

Standard mode

100

kHz

Fast mode

400

kHz

Fast mode plus

1

MHz

f(SCL)

SCL Clock Frequency

High-speed mode (write operation), CB – 100 pF max

3.4

MHz

High-speed mode (read operation), CB – 100 pF max

3.4

MHz

High-speed mode (write operation), CB – 400 pF max

1.7

MHz

High-speed mode (read operation), CB – 400 pF max

1.7

MHz

Standard mode

4.7

μs

Bus Free Time Between a STOP and

tBUF

Fast mode

1.3

μs

START Condition

Fast mode plus

0.5

μs

Standard mode

4

μs

Fast mode

600

ns

Hold Time (Repeated) START

tHD, tSTA

Condition

Fast mode plus

260

ns

High-speed mode

160

ns

(1)

Specified by design. Not tested in production.

4

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