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Not Acknowledge

Acknowledge

Clock Pulse for

Acknowledgement

START

Condition

Data Output

by Transmitter

Data Output

by Receiver

SCL From

Master

Change of Data Allowed

Data Line

Stable;

Data Valid

DATA

CLK

Start

Condition

DATA

Stop

Condition

CLK

TPS62650-Q1

SLVSB62B – MARCH 2012 – REVISED FEBRUARY 2013

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H/S-Mode Protocol

When the bus is idle, both SDA and SCL lines are pulled high by the pull-up devices.

The master generates a start condition followed by a valid serial byte containing HS master code 00001XXX.

This transmission is made in F/S-mode at no more than 400 Kbps. No device is allowed to acknowledge the HS

master code, but all devices must recognize it and switch their internal setting to support 3.4-Mbps operation.

The master then generates a repeated start condition (a repeated start condition has the same timing as the start

condition). After this repeated start condition, the protocol is the same as F/S-mode, except that transmission

speeds up to 3.4 Mbps are allowed. A stop condition ends the HS-mode and switches all the internal settings of

the slave devices to support the F/S-mode. Instead of using a stop condition, repeated start conditions are used

to secure the bus in HS-mode.

Attempting to read data from register addresses not listed in this section results in FFh being read out.

Figure 50. START and STOP Conditions

Figure 51. Bit Transfer on the Serial Interface

Figure 52. Acknowledge on the I2C Bus

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