CS

DOUT

DIN

SCLK

ADD3

WRITE

REPEAT

CH0

CH1

CH2

CH3

EXT_REF

STANDBY

TMP_AVG

ADD2

6

ADD1

ADD0

DB11

DB10

DB2

DB1

DB0

3-State

5

4

3

2

1

13

14

15

16

3-State

Start of Sampling

ADS8028

www.ti.com

SBAS549B – MAY 2011 – REVISED MARCH 2012

SERIAL INTERFACE

Figure 33 shows a detailed ADS8028 serial interface timing diagram. The device uses the serial clock (SCLK) for

internal conversion and for data transfer into and out of the device.

The CS signal defines one frame of conversion and serial transfer. The ADS8028 samples the analog input on

the CS falling edge. The sample-and-hold circuit enters into hold mode and the serial data bus comes out of 3-

state. The subsequent 16 SCLK cycles are used for conversion and data transfer. As shown in Figure 33, the

MUX selects the programmed channel and the sample-and-hold circuit enters into hold mode on the 14th SCLK

falling edge. The DOUT pin goes back to 3-state on the 16th SCLK falling edge or on the CS rising edge

(whichever occurs first). For a valid read or write operation to the ADS8028, 16 clocks must be provided on the

SCLK pin between the CS falling edge to the subsequent CS rising edge. If the CS rising edge occurs before 16

SCLKs have elapsed, the conversion is terminated, the DOUT line goes back into 3-state, and the Control

Register is not updated.

Figure 33. Serial Interface Timing Diagram

Refer to Table 3 for the ADS8028 output data format. Bits ADD[3:0] specify the channel selected for conversion

and bits DB[11:0] are the conversion result for the selected channel.

A CS falling edge brings the DOUT pin out of 3-state and also outputs the ADD3 bit on the DOUT pin. The next

15 bits of data (ADD2 to DB0) are clocked out on the subsequent SCLK falling edges. Therefore, the first SCLK

falling edge outputs the ADD2 bit on DOUT and can also be used by the microcontroller or digital signal

processor (DSP) to read the first bit (ADD3). Similarly, bit DB0 is clocked out on the 15th SCLK falling edge and

can be read by the microcontroller or DSP on the 16th SCLK falling edge. The 16th SCLK falling edge also puts

the DOUT pin into 3-state.

When using a slower SCLK, it may be possible for the microcontroller or DSP to read the data on each SCLK

rising edge. The first SCLK rising edge (after the CS falling edge) reads ADD3 and the 15th SCLK rising edge

reads DB0.

Data provided on the DIN pin are clocked into the ADS8028 on the first 16 SCLK falling edges (after the CS

falling edge). However, if the WRITE bit is not set to '1', the ADS8028 ignores the subsequent 15 bits of data

(refer to the Data Write Operation section for more details).

Copyright © 2011–2012, Texas Instruments Incorporated

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