ADS8028

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SBAS549B – MAY 2011 – REVISED MARCH 2012

DATA READ OPERATION

Table 3 shows the ADS8028 output data format. Bits ADD[3:0] specify the channel selected for conversion and

bits DB[11:0] are the conversion result for the selected channel.

Table 3. Channel Address Bits

ADD3

ADD2

ADD1

ADD0

ANALOG INPUT CHANNEL

0

0

0

0

AIN0

0

0

0

1

AIN1

0

0

1

0

AIN2

0

0

1

1

AIN3

0

1

0

0

AIN4

0

1

0

1

AIN5

0

1

1

0

AIN6

0

1

1

1

AIN7

1

0

0

0

TSENSE without averaging

1

0

0

1

TSENSE with averaging

Analog Input Channel

A CS falling edge brings the DOUT pin out of 3-state and also outputs the ADD3 bit on the DOUT pin. The next

15 bits of data (ADD2 to DB0) are clocked out on the subsequent SCLK falling edges. Therefore, the first SCLK

falling edge outputs the ADD2 bit on DOUT and can also be used by the microcontroller or DSP to read the first

bit (ADD3). Similarly, bit DB0 is clocked out on the 15th SCLK falling edge and can be read by the

microcontroller or DSP on the 16th SCLK falling edge. The 16th SCLK falling edge also puts the DOUT pin into

3-state.

When using a slower SCLK, it may be possible for the microcontroller or DSP to read the data on each SCLK

rising edge. The first SCLK rising edge (after the CS falling edge) reads ADD3 and the 15th SCLK rising edge

reads DB0.

Copyright © 2011–2012, Texas Instruments Incorporated

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