Table 5-1. Pin Attributes (continued)

PIN

SIGNAL NAME

TYPE

DIR (I/O)

VOLTAGE

LEVEL

SHUTDOW

N STATE

STATE

AFTER

POWER-

UP

DESCRIPTION

31

DIG_LDO_OUT

Analog

O

Digital LDO output to

decoupling capacitor

32

VDD_MAIN_IN

POW

1.8 V supply input for SRAM

and digital

33

nRESET

Digital

I

VIO

PD

PD

Reset line for enabling or

disabling device (active low)

34

SLOW_CLK_IN

Digital

I

VIO

PD

PD

32.768-kHz RTC clock input

35

VPP_IN

POW

1.8 V OTP programming input

supply

36

FAST_CLK_REQ

Digital

O

VIO

PD

PD

Fast clock request from the

device

37

NC

NC

Connect to GND

38

NC

NC

Connect to GND

39

PA_LDO_IN

POW

3.3 V supply for PA

40

PA_LDO_IN

POW

3.3 V supply for PA

1. All digital I/O's (with the exception of SDIO signals) are Hi-Z when the device is in shutdown mode with

internal PU/PD according to the "shutdown state" column.

2. See software release notes for support level.

3. LOGGER and HOST_IRQ_WL pins are sensed by the device during boot, see CC33xx Hardware

Integration.

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CC3301, CC3300

SWRS294D – MARCH 2023 – REVISED DECEMBER 2023

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