6.15.2 SPI Timing Specifications

SPI is another host interface for WLAN. The CC330x device also supports shared SPI interface for both BLE and

WLAN.

6.15.2.1 SPI Timing Diagram

tHigh/Low

tHigh/Low

CS

(inverted)

CS

tCS_SU

tISU

tIH

tDr

SCLK

(SPO = 0)

PICO

SCLK

(SPO = 1)

POCI

1 / fclock

Peripheral Mode, SPH = 0

CS

(inverted)

CS

tCS_SU

tISU

tIH

tDr

SCLK

(SPO = 0)

PICO

SCLK

(SPO = 1)

POCI

1 / fclock

tHigh/Low

tHigh/Low

Peripheral Mode, SPH = 1

tTHL/TLH

tTHL/TLH

Figure 6-5. SPI Timing

6.15.2.2 SPI Timing Parameters

PARAMETER

DESCRIPTION

MIN

MAX

UNIT

fclock

Clock frequency, CLK

26

MHz

tHigh

High Period

10

ns

tLow

Low Period

10

tTLH

Rise time, CLK

3

tTHL

Fall time, CLK

3

tCSsu

CS Setup time, CS valid before CLK ↑

3

tISU

PICO, input valid before CLK ↑

3

tIH

PICO Hold time, input valid after CLK ↑

3

tDr, tDf - Active

Delay time, CLK ↑/↓ to output valid

2

10

tDr, tDf - Sleep

Delay time, CLK ↑/↓ to output valid

12

CL

Capacitive load on outputs

15

40

pF

CC3300MOD, CC3301MOD

SWRS333A – JULY 2025 – REVISED AUGUST 2025

www.ti.com

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