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ADS1113 Datasheet(PDF) 8 Page - Texas Instruments |
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ADS1113 Datasheet(HTML) 8 Page - Texas Instruments |
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8 / 43 page ![]() SCLK CS DIN DOUT t SCLK t CSSC t SPWH t DIHD t SPWL t CSDOZ t DOHD t DOPD t SCCS t SCSC t CSH t CSDOD t DIST Hi-Z Hi-Z 8 ADS1018 SBAS526D – NOVEMBER 2012 – REVISED SEPTEMBER 2019 www.ti.com Product Folder Links: ADS1018 Submit Documentation Feedback Copyright © 2012–2019, Texas Instruments Incorporated (1) CS can be tied low permanently in case the serial bus is not shared with any other device. (2) Holding SCLK low longer than 28 ms resets the SPI interface. 7.6 Timing Requirements: Serial Interface over operating ambient temperature range and VDD = 2 V to 5.5 V (unless otherwise noted) MIN MAX UNIT tCSSC Delay time, CS falling edge to first SCLK rising edge(1) 100 ns tSCCS Delay time, final SCLK falling edge to CS rising edge 100 ns tCSH Pulse duration, CS high 200 ns tSCLK SCLK period 250 ns tSPWH Pulse duration, SCLK high 100 ns tSPWL Pulse duration, SCLK low(2) 100 ns 28 ms tDIST Setup time, DIN valid before SCLK falling edge 50 ns tDIHD Hold time, DIN valid after SCLK falling edge 50 ns tDOHD Hold time, SCLK rising edge to DOUT invalid 0 ns 7.7 Switching Characteristics: Serial Interface over operating ambient temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tCSDOD Propagation delay time, CS falling edge to DOUT driven DOUT load = 20 pF || 100 k Ω to GND 100 ns tDOPD Propagation delay time, SCLK rising edge to valid new DOUT DOUT load = 20 pF || 100 k Ω to GND 0 50 ns tCSDOZ Propagation delay time, CS rising edge to DOUT high impedance DOUT load = 20 pF || 100 k Ω to GND 100 ns Figure 1. Serial Interface Timing |
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