ADS5525 datasheet(32/60 Pages) TI2

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APPLICATION INFORMATION

THEORY OF OPERATION

ANALOG INPUT

Resr

200 W

Lpkg

6nH

25 W

Sampling

Capacitor

Csamp

3.2pF

INP

INM

Cbond

2pF

50 W

Cpar1

0.8pF

Ron

10 W

Cpar2

1pF

Ron

15 W

Ron

15 W

Cpar2

1pF

50 W

4pF

Lpkg

6nH

25 W

Cbond

2pF

Resr

200 W

Csamp

3.2pF

Sampling

Capacitor

Sampling

Switch

Sampling

Switch

R-C-RFilter

ADS5525

SLWS191B – JULY 2006 – REVISED MAY 2007

ADS5525 is a low power 12-bit 170 MSPS pipeline ADC in a CMOS process. ADS5525 is based on switched

capacitor technology and runs off a single 3.3-V supply. The conversion process is initiated by a rising edge of

the external input clock. Once the signal is captured by the input sample and hold, the input sample is

sequentially converted by a series of lower resolution stages, with the outputs combined in a digital correction

logic block. At every clock edge, the sample propagates through the pipeline resulting in a data latency of 14

clock cycles. The output is available as 12-bit data, in DDR LVDS or CMOS and coded in either straight offset

binary or binary 2’s complement format.

The analog input consists of a switched-capacitor based differential sample and hold architecture, shown in

Figure 41.

This differential topology results in good ac-performance even for high input frequencies at high sampling rates.

The INP and INM pins have to be externally biased around a common-mode voltage of 1.5 V, available on VCM

pin 13. For a full-scale differential input, each input pin (INP, INM) has to swing symmetrically between VCM +

0.5 V and VCM – 0.5 V, resulting in a 2-VPP differential input swing. The maximum swing is determined by the

internal reference voltages REFP (2.5 V nominal) and REFM (0.5 V, nominal).

Figure 41. Input Stage

The input sampling circuit has a 3-dB bandwidth that extends up to 500 MHz, see Figure 42 (measured from the

input pins to the voltage across the sampling capacitors).

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