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ADS5525 Datasheet(PDF) 12 Page - Texas Instruments |
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ADS5525 Datasheet(HTML) 12 Page - Texas Instruments |
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12 / 60 page  www.ti.com (1/3) AVDD (1/3) AVDD ToParallelPin R AVDD AVDD GND R R (2/3) AVDD (2/3) AVDD ADS5525 SLWS191B – JULY 2006 – REVISED MAY 2007 Table 2. Priority Between Parallel Pins and Serial Registers PIN FUNCTIONS SUPPORTED PRIORITY When using the serial interface, bit <REF> (register 0x6D, bit D4) controls this mode, ONLY MODE Internal/External reference if the MODE pin is tied low. When using the serial interface, bit <DF> (register 0x63, bit D3) controls this mode, ONLY if DATA FORMAT the DFS pin is tied low. DFS LVDS/CMOS When using the serial interface, bit <ODI> (register 0x6C, bits D3-D4) controls LVDS/CMOS selection independent of the state of DFS pin Figure 4. Simple Scheme to Configure Parallel Pins 12 Submit Documentation Feedback |
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