ADS5525 datasheet(7/60 Pages) TI2

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DIGITAL CHARACTERISTICS

(1)

TIMING CHARACTERISTICS – LVDS AND CMOS MODES

(1)

ADS5525

SLWS191B – JULY 2006 – REVISED MAY 2007

The DC specifications refer to the condition where the digital outputs are not switching, but are permanently at a valid logic

level 0 or 1 AVDD = DRVDD = 3.3 V, I

O = 3.5 mA, RL = 100 Ω

(2)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

DIGITAL INPUTS

High-level input voltage

2.4

Low-level input voltage

0.8

High-level input current

µA

Low-level input current

–33

µA

Input capacitance

DIGITAL OUTPUTS – CMOS MODE

High-level output voltage

3.3

Low-level output voltage

Output capacitance

Output capacitance inside the device, from each output to

ground

DIGITAL OUTPUTS – LVDS MODE

High-level output voltage

1375

Low-level output voltage

1025

Output differential voltage, |VOD|

225

350

VOS Output offset voltage, single-ended

Common-mode voltage of OUTP and OUTM

1200

Output capacitance inside the device, from either output to

Output capacitance

ground

(1)

All LVDS and CMOS specifications are characterized, but not tested at production.

(2)

IO refers to the LVDS buffer current setting, RL is the differential load resistance between the LVDS output pair.

Typical values are at 25

°C, min and max values are across the full temperature range T

MIN = –40°C to TMAX = 85°C, AVDD =

DRVDD = 3.3 V, sampling frequency = 170 MSPS, sine wave input clock, 1.5 V

PP clock amplitude, CL = 5 pF

(2), I

O = 3.5 mA,

L = 100 Ω

(3), no internal termination, unless otherwise noted.

For timings at lower sampling frequencies, see the Output Timing section in the APPLICATION INFORMATION of this data

sheet.

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Aperture delay

1.2

Aperture jitter

150

fs rms

Time to valid data after coming out of

100

STANDBY mode

Wake-up time

µs

Time to valid data after stopping and

100

restarting the input clock

clock

Latency

cycles

(1)

Timing parameters are specified by design and characterization and not tested in production.

(2)

CL is the effective external single-ended load capacitance between each output pin and ground.

(3)

IO refers to the LVDS buffer current setting; RL is the differential load resistance between the LVDS output pair.

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