ADS5525 datasheet(4/60 Pages) TI2

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ELECTRICAL CHARACTERISTICS

ADS5525

SLWS191B – JULY 2006 – REVISED MAY 2007

Typical values are at 25

°C, min and max values are across the full temperature range T

MIN = –40°C to TMAX = 85°C,

AVDD = DRVDD = 3.3 V, sampling rate = 170 MSPS, sine wave input clock, 1.5 V

PP differential clock amplitude, 50% clock

duty cycle, –1 dBFS differential analog input, internal reference mode, db gain, DDR LVDS data output (unless otherwise

noted)

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

RESOLUTION

bits

ANALOG INPUT

Differential input voltage range

VPP

Differential input capacitance

Analog input bandwidth

–3 dB, source impedance 50

Ω

500

MHz

Analog input common mode current

280

µA

(per input pin)

REFERENCE VOLTAGES

V(REFB)

Internal reference bottom voltage

Internal reference mode

0.5

V(REFT)

Internal reference top voltage

Internal reference mode

2.5

∆V

(REF)

Internal reference error

V(REFT) - V(REFB)

-60

±25

VCM

Common mode output voltage

Internal reference mode

1.5

VCM output current capability

Internal reference mode

±4

DC ACCURACY

No Missing Codes

Assured

DNL

Differential non-linearity

–0.6

0.5

0.6

LSB

INL

Integral non-linearity

-1.6

± 1

1.6

LSB

Offset error

-10

Offset temperature coefficient

0.002

ppm/

°C

Gain error due to internal reference error alone

(

∆V

(REF)/ 2.0V) %

-3

±1

%FS

Gain error excluding internal reference error(1)

-2

±1

%FS

Gain temperature coefficient

0.01

∆%/°C

PSRR

DC Power supply rejection ratio

0.6

mV/V

POWER SUPPLY

I(AVDD)

Analog supply current

281

LVDS mode, IO = 3.5 mA,

I(DRVDD)

Digital supply current

RL = 100 Ω, CL = 5 pF

ICC

Total supply current

LVDS mode

332

Total power dissipation

LVDS mode

1.1

1.275

In STANDBY mode with input clock

Standby power

100

150

stopped

Clock stop power

With input clock stopped

100

150

(1)

Gain error is specified from design and characterization; it is not tested in production.

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