ADS5525 datasheet(11/60 Pages) TI2

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DEVICE CONFIGURATION

PARALLEL CONFIGURATION ONLY

SERIAL INTERFACE CONFIGURATION ONLY

CONFIGURATION USING BOTH THE SERIAL INTERFACE AND PARALLEL CONTROLS

ADS5525

SLWS191B – JULY 2006 – REVISED MAY 2007

ADS5525 offers flexibility with several programmable features that are easily configured.

The device can be configured independently using either a parallel interface control or a serial interface

programming.

In addition, the device supports a third configuration mode, where both the parallel interface and the serial

control registers are used. In this mode, the priority between the parallel and serial interfaces is determined by a

priority table (Table 2). If this additional level of flexibility is not required, the user can select either the serial

interface programming or the parallel interface control.

To place the device in parallel configuration mode, keep RESET tied to high (DRVDD). Pins DFS, MODE, SEN,

SCLK and SDATA are used to directly control certain modes of the ADC. The device is configured by connecting

the parallel pins to the correct voltage levels (as described in Table 3 to Table 7). The voltage levels can be

derived by using a resistor string as illustrated in Figure 4.There is no need to apply reset.

In this mode, SEN, SCLK and SDATA function as parallel interface control pins. Frequently used functions are

controlled in this mode—standby, selection between LVDS/CMOS output format, internal/external reference,

two's complement/straight binary output format, and position of the output clock edge.

Table 1 has a description of the modes controlled by the four parallel pins.

Table 1. Parallel Pin Definition

CONTROL MODES

DFS

DATA FORMAT and the LVDS/CMOS output interface

MODE

Internal or external reference

SEN

CLKOUT edge programmability

SCLK

LOW SPEED mode control for low sampling frequencies (< 50 MSPS)

SDATA

STANDBY mode – Global (ADC, internal references and output buffers are powered down)

To exercise this mode, the serial registers must first be reset to their default values, and the RESET pin must be

kept low. In this mode, SEN, SDATA, and SCLK function as serial interface pins and are used to access the

internal registers of ADC. The registers are reset either by applying a pulse on the RESET pin, or by a high

setting on the <RST> bit (D1 in register 0x6C). The serial interface section describes the register programming

and register reset in more detail.

Since the parallel pins DFS and MODE are not used in this mode, they must be tied to ground.

For increased flexibility, an additional configuration mode is supported. A combination of serial interface registers

and parallel pin controls (DFS, MODE) are used to configure the device.

To exercise this mode, the serial registers must first be reset to their default values, and the RESET pin must be

kept low. In this mode, SEN, SDATA, and SCLK function as serial interface pins and are used to access the

internal registers of ADC. The registers are reset either by applying a pulse on RESET pin or by a high setting

on the <RST> bit (D1 in register 0x6C). The serial interface section describes the register programming and

The parallel interface control pins DFS and MODE are used, and their function is determined by the appropriate

voltage levels as described in Table 6 and Table 7. The voltage levels can be derived by using a resistor string

as illustrated in Figure 4. Since some functions are controlled using both the parallel pins and serial registers,

the priority between the two is determined by a priority table (Table 2).

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