VN7140AS datasheet(43/45 Pages) STMICROELECTRONICS

43 / 45 page

List of figures

Figure 1.

Block diagram .................................................................... 3

Figure 2.

Configuration diagram (top view)........................................................ 4

Figure 3.

Current and voltage conventions........................................................ 5

Figure 4.

IOUT/ISENSE versus IOUT ............................................................ 12

Figure 5.

Current sense accuracy versus IOUT .................................................... 13

Figure 6.

Switching time and Pulse skew ........................................................ 13

Figure 7.

MultiSense timings (current sense mode)................................................. 14

Figure 8.

Multisense timings (chip temperature and VCC sense mode) (VN7140AJ only) ....................... 14

Figure 9.

TDSTKON ....................................................................... 15

Figure 10.

Latch functionality - behavior in hard short-circuit condition (TAMB << TTSD) ......................... 16

Figure 11.

Latch functionality - behavior in hard short-circuit condition..................................... 17

Figure 12.

Latch functionality - behavior in hard short-circuit condition (autorestart mode + latch off) ................ 17

Figure 13.

Standby mode activation ............................................................ 18

Figure 14.

Standby state diagram.............................................................. 18

Figure 15.

OFF-state output current ............................................................ 19

Figure 16.

Standby current .................................................................. 19

Figure 17.

IGND(ON) vs. Tcase ................................................................ 19

Figure 18.

Logic Input high level voltage ......................................................... 19

Figure 19.

Logic Input low level voltage.......................................................... 20

Figure 20.

High level logic input current.......................................................... 20

Figure 21.

Low level logic input current .......................................................... 20

Figure 22.

Logic Input hysteresis voltage......................................................... 20

Figure 23.

FaultRST Input clamp voltage......................................................... 20

Figure 24.

Undervoltage shutdown ............................................................. 20

Figure 25.

On-state resistance vs. Tcase ......................................................... 21

Figure 26.

On-state resistance vs. VCC ......................................................... 21

Figure 27.

Turn-on voltage slope .............................................................. 21

Figure 28.

Turn-off voltage slope .............................................................. 21

Figure 29.

Won vs. Tcase ................................................................... 21

Figure 30.

Woff vs. Tcase ................................................................... 21

Figure 31.

ILIMH vs. Tcase ................................................................... 22

Figure 32.

OFF-state open-load voltage detection threshold ........................................... 22

Figure 33.

Vsense clamp vs. Tcase ............................................................. 22

Figure 34.

Vsenseh vs. Tcase ................................................................. 22

Figure 35.

Maximum turn off current versus inductance............................................... 24

Figure 36.

PowerSSO-16 on two-layers PCB (2s0p to JEDEC JESD 51-5) ................................. 25

Figure 37.

PowerSSO-16 on four-layers PCB (2s2p to JEDEC JESD 51-7) ................................. 25

Figure 38.

PowerSSO-16 Rthj-amb vs PCB copper area in open box free air condition (one channel on) .............. 26

Figure 39.

PowerSSO-16 thermal impedance junction ambient single pulse (one channel on) .................... 26

Figure 40.

Thermal fitting model of a double-channel HSD in PowerSSO-16 ................................ 27

Figure 41.

S0-8 on two-layers PCB (2s0p to JEDEC JESD 51-5) ........................................ 28

Figure 42.

SO-8 on four-layers PCB (2s2p to JEDEC JESD 51-7) ....................................... 28

Figure 43.

SO-8 Rthj-amb vs PCB copper area in open box free air condition (one channel on) .................... 29

Figure 44.

SO-8 thermal impedance junction ambient single pulse (one channel on) ........................... 29

Figure 45.

Thermal fitting model of a double-channel HSD in SO-8 ....................................... 30

Figure 46.

PowerSSO-16 package outline ........................................................ 31

Figure 47.

SO-8 package outline .............................................................. 33

Figure 48.

PowerSSO-16 reel 13" ............................................................. 34

Figure 49.

PowerSSO-16 carrier tape ........................................................... 35

Figure 50.

PowerSSO-16 schematic drawing of leader and trailer tape .................................... 35

VN7140AJ, VN7140AS

List of figures

DS10830 - Rev 4

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