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DAC60004IDMDR Datasheet(PDF) 18 Page - Texas Instruments |
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DAC60004IDMDR Datasheet(HTML) 18 Page - Texas Instruments |
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18 / 44 page ![]() VOUTA DAC Register DAC Buffer BUF REF BUF Channel A Channel B Channel C Channel D Power Down Logic Resistive Network Power On Reset DACx0004 VOUTB VOUTC VOUTD REFIN SCLK SDIN SYNC GND VDD DAC SDO CLR LDAC POR Copyright © 2016, Texas Instruments Incorporated IN OUT N D V = x REFIN 2 æ ö ç ÷ è ø 2R R 2R S0 2R S1 R 2R S11 2R S12 2R S13 2R S15 REFIN V OUT Buffer Buffer 18 DAC80004, DAC70004, DAC60004 SLASED6D – APRIL 2016 – REVISED DECEMBER 2017 www.ti.com Product Folder Links: DAC80004 DAC70004 DAC60004 Submit Documentation Feedback Copyright © 2016–2017, Texas Instruments Incorporated 8 Detailed Description 8.1 Overview The DAC80004, DAC70004, and DAC60004 are quad-channel, 16-bit, voltage-output DACs with internal reference buffers and output buffers. Each channel consists of an R-2R ladder configuration with the 4 MSBs segmented, followed by an operational amplifier, as shown in Figure 51. The DACx0004 devices have a constant impedance (30 kΩ typical), buffered reference input. The output of the reference buffers drives the R-2R ladders. With the production trim process these devices have excellent dc accuracy and ac performance. Figure 51. DACx0004 Architecture The input coding to the DACx0004 is straight binary, so the ideal output voltage is given by Equation 1: (1) Where: N = resolution in bits; either 16 (DAC80004), 14 (DAC70004) or 12 (DAC60004) DIN = decimal equivalent of the binary code that is loaded to the DAC register. DIN ranges from 0 to 2 N –1 REFIN = DAC reference voltage 8.2 Functional Block Diagram |
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