DAC60004IDMDR datasheet(20/44 Pages) TI2

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SCLK

SYNC

SDIN

DB31

DB0

DB31

DB0

Invalid/Interrupted Write Sequence

Output/Mode Does Not Update on 32

SCLK Falling Edge

Valid Write Sequence

Output/Mode Update on 32

SCLK Falling Edge

Power-On Reset

Undefined

No Power-On Reset

0.0 V

0.7 V

2.4 V

5.5 V

2.7 V

VDD (V)

Specified Supply

Voltage Range

DAC80004, DAC70004, DAC60004

SLASED6D – APRIL 2016 – REVISED DECEMBER 2017

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Product Folder Links: DAC80004 DAC70004 DAC60004

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Figure 52. Relevant Voltage Levels for IPOR Circuit

8.4 Device Functional Modes

8.4.1 Serial Interface

The DACx0004 devices have a 4-wire serial interface: SYNC, SCLK, SDIN, and SDO (see Pin Configuration and

Functions). The serial interface (3-wire and 4-wire) is compatible with SPI, QSPI, and Microwire interface

standards, as well as most DSPs and it operates up to 50 MHz. See the Write Mode Stand-Alone Timing and

Write Mode Daisy-Chain Timing diagrams (see Figure 1 and Figure 2) for examples of typical write and read

sequences. The input shift register is 32 bits wide.

8.4.1.1 Stand-Alone Mode

The serial clock SCLK can be a continuous or a gated clock. The first falling edge of SYNC starts the operation

cycle. When SYNC is high, the SCLK and SDIN signals are blocked and the SDO pin (TSSOP-14 and VSON-14

packages) is in a Hi-Z state. The device internal registers are updated from the shift register on the 32nd falling

edge of SCLK.

8.4.1.1.1

SYNC Interrupt – Stand-Alone Mode

For stand-alone operation, the SYNC line stays low for at least 32 falling edges of SCLK and the addressed DAC

edge, it acts as an interrupt to the write sequence; the shift register resets and the write sequence is discarded.

Neither an update of the data buffer contents, DAC register contents, nor a change in the operating mode occurs

(as shown in Figure 53).

Figure 53. SYNC Interrupt – Stand Alone Operation

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