DAC60004IDMDR datasheet(23/44 Pages) TI2

23 / 44 page

Resistor

Network

Power-Down

Circuitry

R2R Ladder

Amplifier

VOUTX

DAC80004, DAC70004, DAC60004

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SLASED6D – APRIL 2016 – REVISED DECEMBER 2017

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8.4.3 DAC Power-Down Modes

The DACx0004 use four modes of operation. These modes are accessed by setting command bits D28 – D24

and power-down register bits D09 and D08. The command bits must be set to 0100 (see Table 3). Once the

command bits are set correctly, the four different power-down modes are software programmable by setting bits

D09 and D08 in the shift register. Table 5 shows how to control the operating mode with data bits PD1 (D09),

PD0 (D08).

Table 5. Power-Down Bits

POWER DOWN BITS

DESCRIPTION

D09

D08

Normal operation/power up selected channel(s) (Default)

Power down selected channel(s) 1 kΩ-GND

Power down selected channel(s) 100 kΩ-GND

Power down selected channel(s) Hi-Z

It is possible to write to the DAC register/buffer of the DAC channel that is powered down. When the DAC

channel is then powered up, it powers up to this new value.

The advantage of the available power-down modes is that the output impedance of the device is known while it is

in power-down mode. As described in Table 5, there are three different power-down options. VOUTX can be

connected internally to GND through a 1 k

Ω resistor, a 100 kΩ resistor, or open-circuited (Hi-Z). The DAC power-

down circuitry is shown in Figure 57.

Figure 57. DACx0004 Power Down

8.4.4 CLR Pin Functionality and Software CLEAR Mode

The CLR pin is an asynchronous input pin to the DAC. When activated, this falling edge sensitive pin clears the

DAC buffers and the DAC latches to zero, mid, full or user programmed code depending on the clear mode

32nd falling edge of the next write to the device. If the CLR pin receives a falling edge signal during a write

sequence in normal operation, the clear mode is activated and changes the input and DAC registers

immediately. Additionally, all DAC registers can also be cleared via SPI command 1011. Note that the clear

mode bits determine the clear code for all the DACs upon clear operation.

8.4.4.1 DAC Clear Mode Registers

The DACx0004 implement four different clear modes. These modes are accessed by setting command bits

D28 – D24 and clear mode register bits D01 and D00. The command bits must be set to 0101 (see Table 3).

Based on the value of clear mode register (see Table 6), all of the DAC and the buffers are cleared to zero, mid,

or full-scale code, when the CLR pin sees a falling edge or after a software clear command is issued.

The user defined clear scale can be set by writing 16-/14-/12- data to 1001 to bits D28 – D24.

DAC60004IDMDR Datasheet(PDF) 23 Page - Texas Instruments

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