DAC60004IDMDR datasheet(24/44 Pages) TI2

24 / 44 page

DAC80004, DAC70004, DAC60004

SLASED6D – APRIL 2016 – REVISED DECEMBER 2017

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Product Folder Links: DAC80004 DAC70004 DAC60004

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Table 6. Clear Mode Bits

CLEAR MODE BITS

DESCRIPTION

D01

D00

All DACs clear to zero scale (default)

All DACs clear to mid scale

All DACs clear to full scale

8.4.5 LDAC Pin Functionality

The DACx0004 devices offer both a software and hardware simultaneous update and control function. The DAC

double-buffered architecture has been designed so that new data can be entered for each DAC without

disturbing the analog outputs. Data updates can be performed either in synchronous or in asynchronous mode.

In asynchronous mode, the LDAC pin is used as an active low signal for simultaneous DAC updates. Multiple

single-channel writes can be done in order to set different channel buffers to desired values and then pulse the

LDAC pin low to simultaneously update the DAC output registers. Data buffers of all channels must be loaded

with desired data before an LDAC low pulse. After a LDAC low pulse, all DACs are simultaneously updated with

the last contents of the corresponding data buffers. If the content of a data buffer is not changed, the

corresponding DAC output remains unchanged after the LDAC pin is pulsed low.

In synchronous mode, data are updated with the falling edge of the 32nd SCLK cycle, which follows a falling

edge of SYNC. For such synchronous updates, the LDAC pin is not required, and it must be connected to GND

permanently or asserted and held low before sending commands to the device.

8.4.5.1 Software LDAC Mode Registers

Alternatively, all DAC outputs can be updated simultaneously using the built-in software function of LDAC. The

LDAC register offers additional flexibility and control by allowing the selection of which DAC channel(s) should be

updated simultaneously when the LDAC pin is being brought low. The LDAC register is loaded with a 4-bit word

(D03 and D00) using command bits D28 – D24 (see Table 3). The default value for each bit, and therefore for

each DAC channel, is zero. If the LDAC register bit is set to 1, it overrides the LDAC pin (the LDAC pin is

internally tied low for that particular DAC channel), and this DAC channel updates synchronously after the falling

edge of the 32nd SCLK cycle. However, if the LDAC register bit is set to 0, the DAC channel is controlled by the

LDAC pin.

See Table 7 for more information.

Table 7. LDAC Register

LDAC REGISTER BITS (D03 – D00)

DAC UPDATE

Determined by LDAC pin (Default)

DAC channel ignores LDAC pin, DAC updates on 32nd falling edge of SCLK, DAC channels

see LDAC as 0

8.4.6 Software Reset Mode

The DACx0004 implements a software reset feature. The software reset function uses command bits D28 – D24

(see Table 3). Table 1 shows the reset values for different registers.

DAC60004IDMDR Datasheet(PDF) 24 Page - Texas Instruments

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