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DAC80004, DAC70004, DAC60004

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SLASED6D – APRIL 2016 – REVISED DECEMBER 2017

Product Folder Links: DAC80004 DAC70004 DAC60004

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Copyright © 2016–2017, Texas Instruments Incorporated

8.3 Feature Description

8.3.1 Output Amplifier

The DACx0004 output buffer amplifier is capable of generating near rail-to-rail voltages on its output, giving a

maximum output range of 0 V to REFIN. It is capable of driving a load of 5 kΩ in parallel with 2 nF to GND. The

typical slew rate of this amplifier while driving no load is 1.5 V/µs, with a full-scale settling time of 8 µs to 1 LSB

of the final value as shown in Figure 43 and Figure 44. The current consumption of the amplifier (unloaded) is 1

mA/channel (typical). The DACx0004 output amplifier also implements a short circuit current limiting circuit. The

default value of short circuit limit is 40 mA, however this can be reduced to 30 mA using dedicated bits (1 per

channel) via SPI command 1010 (see Table 2).

8.3.2 Reference Buffer

The DACx0004 requires an external reference to operate. The reference input pin has the following input range:

2.2 V to (VDD – 0.2) for 2.7 V ≤ VDD ≤ 4.5 V

2.2 V to VDD for 4.5 V ≤ VDD ≤ 5.5 V

The DACx0004 contains a dedicated reference buffer for each DAC channel. The REFIN pin drives the input of

these buffers. The integrated reference buffers offers constant impedance of 30 kΩ (typical) at the REFIN pin.

This simplifies the external reference drive circuit for the device.

8.3.3 Power-On Reset

The DACx0004 contain a power-on-reset circuit that controls the output voltage during power up. The power-on

reset is useful in applications where it is important to know the state of the output of each DAC while the device

is in the process of powering up. At power up all DAC registers are filled with power-on reset code (see Table 1).

8.3.3.1 POR Pin Feature

The DAC power-on reset code for all of the channels depends on the state of the POR pin at power up (see Pin

Configuration and Functions).

Each DAC channel remains that way until a valid load command is written to it. All device registers are reset at

power up as shown in Table 1.

Table 1. DACx0004 Power-On Reset Values

REGISTER NAME

DACx0004 - POWER-ON RESET VALUE

TSSOP-/VSON-14

DAC latches (per channel)

If POR pin = '0' then Zero Scale else Mid scale

DAC buffers (per channel)

If POR pin= '0' then Zero Scale else Mid scale

Power down (per channel)

00 – Normal mode

Clear mode

00 – Clear to Zero

Ignore LDAC (per channel)

0000 – Do not ignore

Daisy chain

0 – Daisy chain disabled, DAC update at 32nd SCLK falling edge

Short circuit limit (per channel)

0000 – all DACs 40 mA

8.3.3.2 Internal Power-On Reset (IPOR) Levels

When the device powers up, an IPOR circuit sets the device in default mode as shown in Table 1. The IPOR

circuit requires specific VDD levels, as indicated in Figure 52, to ensure discharging of internal capacitors and to

reset the device on power up. In order to ensure a power-on reset, VDD must be below 0.7 V for at least 1 ms.

When VDD drops below 2.4 V but remains above 0.7 V (shown as the undefined region), the device may or may

not reset under all specified temperature and power supply conditions. In this case, In this case a power-down

reset is recommended. When VDD remains above 2.4 V, a power-on reset does not occur.