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L5951 Datasheet(PDF) 5 Page - STMicroelectronics |
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L5951 Datasheet(HTML) 5 Page - STMicroelectronics |
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5 / 18 page ![]() DocID7510 Rev 2 5/18 L5951 Functional description 18 2 Functional description 2.1 General features The L5951 is an integrated circuit which provides a J1850 physical layer as well three voltage regulators. The L5951 was developed to provide the power and Class 2/IDR interface for a microcontroller. 2.2 REG1 output voltage The REG1 regulator output is equal to 3.3V. The 3.3V regulator is non low drop out and can handle currents up to 100mA with short circuit limit of 280mA. 2.3 REG2 output voltage The REG2 regulator output is equal to 5V and can handle currents up to 100mA with short circuit limit of 280mA. The output stage of the 5V regulator is low dropout. 2.4 REG3 output voltage The REG3 regulator output is equal to 7.8 V and can handle currents up to 100mA with short circuit limit of 280 mA. The output stage of the 7.8 V regulator is low dropout. REG3 regulator is controlled by the EN (enable) pin of the IC. REG3 can be turned on and off by toggling the EN pin. A logic "1" on the EN pin enables REG3, while a logic "0" on the EN pin disables REG3. The maximum voltage when REG3 is off must be less than 0.2 V. Sleep(a) Input - The Class 2 transmitter can be turned on and turned off by the Sleep* pin. Once the voltage level is above 2VDC, the transmitter is enabled. If the Sleep* pin drops below 0.8 VDC, and EN is "0" the transceiver goes into a low power mode. In low power mode, REG3 and the transceiver are disabled. The L5951 will still receive messages and send them to the microcontroller out of the RX pin. LVS input - Reg1 and Reg2 are supplied by Vbat pin. The device could then dissipate a lot of power, causing thermal shutdown at high voltage. For this reason a secondary low voltage supply (LVS) can be used to reduce power dissipation. Reset(a) Output - The L5951 has low voltage or no voltage circuitry that is a warning to the microcontroller. If REG2 drops 0.3 VDC below its normal operating voltage, the Reset(a) pin will go to a logic "0". Between the voltage levels of 4.65 VDC (min) and 5.10 VDC (max) on REG2, a reset will occur. There is a hysteresis of 50mV on the Reset(a) pin. Low Input Voltage Operation - If battery voltage level drops below 7.0V, the outputs are to remain alive and ready for the return of normal voltage battery levels. The L5951 will be able to retrieve data off the BUS and send it to the microprocessor when the supply voltage is as low as 4.9 V. The regulators should stay the same voltage as the battery voltage down to 7.0 V minus operating headroom for the 7.8 V regulator. BUS VOH,min are not guaranteed over all conditions below VBAT = 9.0 V. a. denotes active low Obsolete Product(s) - Obsolete Product(s) |
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