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INA821 Datasheet(PDF) 1 Page - Texas Instruments |
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INA821 Datasheet(HTML) 1 Page - Texas Instruments |
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1 / 51 page  INA819 35-μV Offset, 8-nV/√Hz Noise, Low-Power, Precision Instrumentation Amplifier 1 Features • Low offset voltage: 10 µV (typ), 35 µV (max) • Gain drift: 5 ppm/°C (G = 1), 35 ppm/°C (G > 1) (max) • Noise: 8 nV/√ Hz • Bandwidth: 2 MHz (G = 1), 270 kHz (G = 100) • Stable with 1-nF capacitive loads • Inputs protected up to ±60 V • Common-mode rejection: 110 dB, G = 10 (min) • Power supply rejection: 110 dB, G = 1 (min) • Supply current: 385 µA (max) • Supply range: – Single supply: 4.5 V to 36 V – Dual supply: ±2.25 V to ±18 V • Specified temperature range: –40°C to +125°C • Packages: 8-pin SOIC, VSSOP, WSON 2 Applications • Analog input module • Flow transmitter • Battery test • LCD test • Electrocardiogram (ECG) • Surgical equipment • Process analytics (pH, gas, concentration, force and humidity) 3 Description The INA819 is a high-precision instrumentation amplifier that offers low power consumption and operates over a very wide single-supply or dual- supply range. A single external resistor sets any gain from 1 to 10,000. The device offers high precision as a result of super-beta input transistors, which provide exceptionally low input offset voltage, offset voltage drift, input bias current, input voltage, and current noise. Additional circuitry protects the inputs against overvoltage up to ±60 V. The INA819 is optimized to provide a high common- mode rejection ratio. At G = 1, the common-mode rejection ratio exceeds 90 dB across the full input common-mode range. The device is designed for low- voltage operation from a 4.5-V single supply, as well as dual supplies up to ±18 V. The INA819 is available in 8-pin SOIC, VSSOP, and WSON packages, and is specified over the –40°C to +125°C temperature range. Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) INA819 SOIC (8) 4.90 mm × 3.91 mm VSSOP (8) 3.00 mm × 3.00 mm WSON (8) 3.00 mm × 3.00 mm (1) For all available packages, see the package option addendum at the end of the data sheet. + – + – + – 40 k 40 k 40 k 40 k Overvoltage Protection RG REF +VS OUT –VS –IN +IN RG RG Overvoltage Protection 25 k 25 k VO = G(V+IN – V–IN) + VREF G = 1 + RG 50 k INA819 Simplified Internal Schematic Input Stage Offset Voltage Drift (PV/qC) 0 2.5% 5% 7.5% 10% 12.5% 15% 17.5% 20% 22.5% 25% -0.4 0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 D002 Typical Distribution of Input Stage Offset Voltage Drift INA819 SBOS959D – DECEMBER 2018 – REVISED APRIL 2022 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. |
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