AD3530 datasheet(45/49 Pages) AD

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Data Sheet

AD3530/AD3530R

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Table 36. Bit Descriptions for MULTI_DAC_SEL_0

Bits

Bit Name

Description

Reset

Access

MD_SEL_CH_7

Multiple DAC Select Channel 7. If selected, write operation on MULTI_DAC_CH also writes DAC_CH7 with the

same data. If deselected, write operation on MULTI_DAC_CH will have no effect on DAC_CH7.

0x1

R/W

0: MD Sel 0. Deselect DAC_CH7 for MULTI_DAC_CH operation.

1: MD Sel 1. Select DAC_CH7 for MULTI_DAC_CH operation.

MD_SEL_CH_6

Multiple DAC Select Channel 6. If selected, write operation on MULTI_DAC_CH also writes DAC_CH6 with the

same data. If deselected, write operation on MULTI_DAC_CH will have no effect on DAC_CH6.

0x1

R/W

0: MD Sel 0. Deselect DAC_CH6 for MULTI_DAC_CH operation.

1: MD Sel 1. Select DAC_CH6 for MULTI_DAC_CH operation.

MD_SEL_CH_5

Multiple DAC Select Channel 5. If selected, write operation on MULTI_DAC_CH also writes DAC_CH5 with the

same data. If deselected, write operation on MULTI_DAC_CH will have no effect on DAC_CH5.

0x1

R/W

0: MD Sel 0. Deselect DAC_CH5 for MULTI_DAC_CH operation.

1: MD Sel 1. Select DAC_CH5 for MULTI_DAC_CH operation.

MD_SEL_CH_4

Multiple DAC Select Channel 4. If selected, write operation on MULTI_DAC_CH also writes DAC_CH4 with the

same data. If deselected, write operation on MULTI_DAC_CH will have no effect on DAC_CH4.

0x1

R/W

0: MD Sel 0. Deselect DAC_CH4 for MULTI_DAC_CH operation.

1: MD Sel 1. Select DAC_CH4 for MULTI_DAC_CH operation.

MD_SEL_CH_3

Multiple DAC Select Channel 3. If selected, write operation on MULTI_DAC_CH also writes DAC_CH3 with the

same data. If deselected, write operation on MULTI_DAC_CH will have no effect on DAC_CH3.

0x1

R/W

0: MD Sel 0. Deselect DAC_CH3 for MULTI_DAC_CH operation.

1: MD Sel 1. Select DAC_CH3 for MULTI_DAC_CH operation.

MD_SEL_CH_2

Multiple DAC Select Channel 2. If selected, write operation on MULTI_DAC_CH also writes DAC_CH2 with the

same data. If deselected, write operation on MULTI_DAC_CH will have no effect on DAC_CH2.

0x1

R/W

0: MD Sel 0. Deselect DAC_CH2 for MULTI_DAC_CH operation.

1: MD Sel 1. Select DAC_CH2 for MULTI_DAC_CH operation.

MD_SEL_CH_1

Multiple DAC Select Channel 1. If selected, write operation on MULTI_DAC_CH also writes DAC_CH1 with the

same data. If deselected, write operation on MULTI_DAC_CH will have no effect on DAC_CH1.

0x1

R/W

0: MD Sel 0. Deselect DAC_CH1 for MULTI_DAC_CH operation.

1: MD Sel 1. Select DAC_CH1 for MULTI_DAC_CH operation.

MD_SEL_CH_0

Multiple DAC Select Channel 0. If selected, write operation on MULTI_DAC_CH also writes DAC_CH0 with the

same data. If deselected, write operation on MULTI_DAC_CH will have no effect on DAC_CH0.

0x1

R/W

0: MD Sel 0. Deselect DAC_CH0 for MULTI_DAC_CH operation.

1: MD Sel 1. Select DAC_CH0 for MULTI_DAC_CH operation.

SOFTWARE LDAC TRIGGER 0 REGISTER

Address: 0xE5, Reset: 0x00, Name: SW_LDAC_TRIG_0

Initiates transfer of INPUT_CHn to DAC_CHn. Only takes effect on enabled channels identified by SW_LDAC_EN_0.

[7] SLD_TRIG_0 (W)

[6:0] RESERVED

Table 37. Bit Descriptions for SW_LDAC_TRIG_0

Bits

Bit Name

Description

Reset

Access

SLD_TRIG_0

Software LDAC Trigger 0. When set, initiates transfer of INPUT_CHn to DAC_CHn, where n is the channel

number as enabled by SW_LDAC_EN_0. Writing 0 will have no effect.

0x0

[6:0]

RESERVED

Reserved.

0x0

MULTIPLE INPUT REGISTER

Address: 0xE6, Reset: 0x0000, Name: MULTI_INPUT_CH

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