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AD3530 Datasheet(PDF) 10 Page - Analog Devices

Part # AD3530
Description  8-Channel, 16-Bit Voltage Output DACs, On-Chip Reference, SPI
PDF  49 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

AD3530 Datasheet(HTML) 10 Page - Analog Devices

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Data Sheet
AD3530/AD3530R
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
analog.com
Rev. A | 10 of 49
Figure 5. LFCSP Pin Configuration
Figure 6. WLCSP Pin Configuration
Table 8. Pin Function Descriptions
Pin No.
Mnemonic
Type
Description
LFCSP
WLCSP
1
A1
MUX_OUT
AO
Analog Multiplexer. The MUX_OUT pin is used to monitor the internal die temperature, output voltages and output current
of a selected channel.
2, 6
B1, B2,
D2
VDD
S
Power Supply Input. The AD3530/AD3530R operate from 2.7V to 5.5V. Decouple the VDD supply with a 10µF capacitor in
parallel with a 0.1µF capacitor to GND.
3
C3
IOVDD
DI
Digital Power Supply. The voltage on the IOVDD pin is specified in Table 2.
4
B3, C1,
C2, D3,
E1
GND
S
Ground Reference Point for All Circuitry on the Device.
5
D1
VREF
AI/O
Reference Output Voltage. When using the internal reference, this is the reference output pin. The VREF is the reference
input by default.
7
E2
VOUT7
AO
Analog Output Voltage from DAC 7. The output amplifier has rail-to-rail operation.
8
E3
VOUT6
AO
Analog Output Voltage from DAC 6. The output amplifier has rail-to-rail operation.
9
E4
VOUT5
AO
Analog Output Voltage from DAC 5. The output amplifier has rail-to-rail operation.
10
D4
VOUT4
AO
Analog Output Voltage from DAC 4. The output amplifier has rail-to-rail operation.
11
E5
SDI
DI
Serial Data Input (Logic Input). Provides data to be written to the device and is clocked into the register on the rising edge
of SCLK.
12
D5
CSB
DI
Active-Low Control Input. This is the frame synchronization signal for the input data.
13
C4
RESETB
DI
Asynchronous Reset Pin. Active-low logic input and falling edge sensitive. See the Hardware Reset section for additional
information.
14
C5
SDO
DO
Serial Data Output (Logic Output). A readback operation provides data on this output pin as a serial data stream. Data is
clocked out on the falling edge of SCLK and is valid on the rising edge of SCLK.
15
B5
SCLK
DI
Serial Clock Input. Data transfers at rates of up to 50MHz for write and read operations.
16
A5
LDACB
DI
Asynchronous Load DAC Pin. Active-low logic input, falling edge sensitive. See the Hardware LDAC section for additional
information.
17
B4
VOUT0
AO
Analog Output Voltage from DAC 0. The output amplifier has rail-to-rail operation.



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