RT7296F

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is a registered trademark of Richtek Technology Corporation.

www.richtek.com

DS7296F-06

September

2023

14

Figure 5. Derating Curve of Maximum Power

Dissipation

Layout Considerations

For best performance of the RT7296F, the following

layout guidelines must be strictly followed.



Input capacitor must be placed as close to the IC as

possible.



SW should be connected to inductor by wide and

short trace. Keep sensitive components away from

this trace.



Keep VIN, GND and SW traces connected to pin as

wide as possible for improving thermal dissipation.

SW

VOUT

R1

R2

CIN

CIN COUT

COUT

Via can help to reduce

power trace and improve

thermal dissipation.

The feedback components

must be connected as close

to the device as possible.

VOUT

GND

PG

SW

FB

EN/SYNC

BOOT

VIN

PVCC

GND

Css

Input capacitor must be placed as close

to the IC as possible. Suggestion layout

trace wider for thermal.

PVCC

R5

Keep the SW trace as physically short and wide as

practical to minimize radiated emissions and enables

better thermal

Figure 6. PCB Layout Guide

0.0

0.3

0.6

0.9

1.2

1.5

0

25

50

75

100

125

Ambient Temperature (°C)

Four-Layer PCB