TMP411CD datasheet(25/61 Pages) TI2

25 / 61 page

Note

When a shutdown command is issued, the TMP411/TMP411D device completes the current

conversion before shutting down. The wait time only applies to the 200μs immediately following

shutdown. One-shot commands can be issued without delay thereafter.

7.5 Programming

7.5.1 Serial Interface

The TMP411/TMP411D operates only as a target device on either the two-wire bus or the SMBus. Connections

to either bus are made through the SDA and SCL open-drain I/O lines. The SDA and SCL pins feature

integrated spike suppression filters and Schmitt triggers that minimize the effects of input spikes and bus noise.

The TMP411/TMP411D supports the transmission protocol for fast (1kHz to 400kHz) and high-speed (1kHz to

3.4MHz) modes. All data bytes are transmitted with the MSB first.

7.5.2 Bus Overview

The TMP411/TMP411D is SMBus interface-compatible. In SMBus protocol, the device that initiates the transfer

is a controller, and the controller controls devices known as targets. The bus must be controlled by a controller

device that generates the serial clock (SCL), controls the bus access, and generates the START and STOP

conditions.

To address a specific device, a START condition is initiated. START is indicated by pulling the data line (SDA)

from a high to low logic level while the SCL line is high. All targets on the bus shift are in the target address byte,

with the last bit indicating if a read or write operation is needed. During the ninth clock pulse, the target that is

addressed responds to the controller by generating an acknowledge bit and pulling the SDA line low.

Data transfer is then initiated and sent over eight clock pulses followed by an acknowledge bit. During data

transfer, the SDA line must remain stable while the SCL is high. A change in the SDA while the SCL is high is

interpreted as a control signal.

Once all data transfers, the controller generates a STOP condition. STOP is indicated by pulling the SDA line

from low to high, while the SCL line is high.

7.5.3 Timing Diagrams

The TMP411/TMP411D is two-wire and SMBus-compatible. Figure 7-4 to Figure 7-7 describe the various

operations on the TMP411/TMP411D. Bus definitions are given below:

Bus Idle: Both SDA and SCL lines remain high.

Start Data Transfer: A change in the state of the SDA line, from high to low (while the SCL line is high) defines

a START condition. A START condition initiates each data transfer.

Stop Data Transfer: A change in the state of the SDA line from low to high (while the SCL line is high) defines a

STOP condition. A STOP or repeated START condition terminates each data transfer.

Data Transfer: The number of data bytes transferred between a START and a STOP condition is not limited and

is determined by the controller device. The receiver acknowledges the data transfer.

Acknowledge: Each receiving device (when addressed) is required to generate an acknowledge bit. A device

that acknowledges must pull the SDA line down during the acknowledge clock pulse so the SDA line is

stable and low during the high period of the acknowledge clock pulse. Setup and hold times must be

taken into account. On a controller receive, the controller signals data transfer termination by generating a

not-acknowledge bit transmitted by the controller.

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TMP411, TMP411D

SBOS383E – DECEMBER 2006 – REVISED JULY 2025

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