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TMP411CD Datasheet(PDF) 11 Page - Texas Instruments |
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TMP411CD Datasheet(HTML) 11 Page - Texas Instruments |
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11 / 61 page ![]() 6.7 Timing Characteristics FAST MODE HIGH-SPEED MODE UNIT MIN MAX MIN MAX f(SCL) SCL operating frequency 0.001 0.4 0.001 3.4 MHz t(BUF) Bus free time between STOP and START condition 600 160 ns t(HDSTA) Hold time after repeated START condition. After this period, the first clock is generated. 100 100 ns t(SUSTA) Repeated START condition setup time 100 100 ns t(SUSTO) STOP condition setup time 100 100 ns t(HDDAT) Data hold time 0(1) 0(2) ns t(SUDAT) Data setup time TMP411 (Legacy chip) 100 10 ns TMP411 (New chip) TMP411D 100 20 t(LOW) SCL clock LOW period 1300 160 ns t(HIGH) SCL clock HIGH period 600 60 ns tF Clock and data fall time 300 160 ns tR Clock and data rise time 300 160 ns SCLK ≤ 100kHz 1000 ns (1) For cases with an SCL fall time of less than 20ns, or an SDA rise or fall time of less than 20ns, the hold time must be greater than 20ns. (2) For cases with an SCL fall time of less than 10ns, or an SDA rise or fall time of less than 10ns, the hold time must be greater than 10ns. 6.8 Two-Wire Timing Diagram t(BUF) SDA SCL P S S t(HDSTA) t(HDDAT) t(HIGH) t(SUSTA) t(SUDAT) t(LOW) t(HDSTA) t(SUSTO) tR tF P Figure 6-1. Two-Wire Timing Diagram www.ti.com TMP411, TMP411D SBOS383E – DECEMBER 2006 – REVISED JULY 2025 Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 11 Product Folder Links: TMP411 TMP411D |
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