ADPL12008/ADPL12010

20V, 8A/10A Fully Integrated Buck Converter

with 20μA Quiescent Current and Dual-Phase

Capability

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Analog Devices | 15

Choose an input capacitor that exhibits less than +10°C self-heating temperature rise at the RMS input current for optimal

long-term reliability. The input-voltage ripple comprises ΔVQ (caused by the capacitor discharge) and ΔVESR (caused by

the ESR of the capacitor). Assume the contribution from the ESR and capacitor discharge is equal to 50%. Calculate the

input capacitance and Equivalent series resistance (ESR) required for a specified input voltage ripple using the following

equations:

ESRIN =

∆VESR

ILOAD(MAX) +

∆IL

2

⁄

CIN =

ILOAD(MAX) × D (1 − D)

∆VQ × fSW

Where:

∆IL =

(

VSUP − VOUT) × VOUT

VSUP × fSW × L

D =

VOUT

VSUP

and ILOAD(MAX) is the maximum output current, ΔIL is the peak-to-peak inductor current, fSW is the switching frequency,

and D is the duty cycle.

Selecting the Inductor

Inductor selection is a compromise between component size, efficiency, control loop bandwidth, and loop stability.

Insufficient inductance increases the inductor current ripple, conduction losses, and output voltage ripple, and causes

loop instability in the worst case. A large inductor reduces the inductor current ripple by sacrificing component size and

slow response. For recommended inductor values, see Table 2 for more details.

Output Capacitor

The output capacitor is a critical component for switching regulators. It is selected to meet the requirements for output

voltage ripple, load transient response, and loop stability.

The output voltage ripple comprises ΔVQ (caused by the capacitor discharge) and ΔVESR (caused by the ESR of the

output capacitor). Use low ESR ceramic capacitors. Assume the contribution to the output ripple voltage from ESR and

the capacitor discharge to be equal. Use the following equations for the output capacitance and ESR for a specified output

voltage ripple.

ESR =

∆VESR

∆IP-P

COUT =

∆IP-P

8 × ∆VQ × fSW

∆IP-P =

(

VSUP − VOUT) × VOUT

VSUP × fSW × L

VOUTRIPPLE = ∆VESR + ∆VQ

Where, ΔIP-P is the peak-to-peak inductor current, and fSW is the switching frequency.

During a load step, the output capacitors supply the load current before the converter loop responds with a higher duty

cycle, which causes the output voltage to undershoot. To keep the maximum output voltage deviations below the tolerable

limits of the electronics being powered, calculate the output capacitance with the following equation:

COUT =

∆ILOAD

∆V × 2π × fC

Where, ΔI is the load step, ΔV is the allowed output voltage undershoot, and fC is the loop crossover frequency, which

can be assumed to be the lesser of fSW/10 or 100kHz. The calculated COUT is the capacitance after considering

capacitance tolerance, temperature effect, and voltage derating. Table 2 shows the recommended values of output

capacitance based on frequency and output voltage.