ADPL12008/ADPL12010

20V, 8A/10A Fully Integrated Buck Converter

with 20μA Quiescent Current and Dual-Phase

Capability

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Analog Devices | 16

PCB Layout Guidelines

1. Careful Printed circuit board (PCB) layout is critical to achieve low switching losses, low EMI, and clean, stable

operation. For example, see Figure 2 for more details.

2. Place the input bypass capacitors CBP and CIN as close as possible to each SUP and PGND on both sides of the IC.

CBP should be placed right next to the SUP and PGND node on the same layer to provide the best EMI rejection and

minimize the input noise on the SUP. The symmetrical CIN and CBP arrangements generate SUP loops with opposite

orientations to cancel the magnetic fields and aid in EMI mitigation.

3. Minimize the connection from the buck output capacitor's ground terminal to the input capacitor's ground terminal.

Keep the buck high-current path, and power traces wide and short. Minimize the traces from the LX node to the

inductor and then to the output capacitors. This minimizes the buck current loop area and minimizes LX trace

resistance and stray capacitance to achieve optimal efficiency.

4. Place the bootstrap capacitor CBST close to the IC. Use short and wide traces from BST and LX, and minimize the

routing parasitic impedance. High parasitic impedance from BST to LX impacts the switching speed, further increases

switching losses, and high dV/dt noise. For the BST to LX routing, see Figure 2.

5. Place the BIAS capacitor as close to the BIAS node as possible. Noise coupling into BIAS can disturb the reference

and bias circuitry if this capacitor is installed away from the IC.

6. Keep the sensitive analog signals (FB/VEA) away from noisy switching nodes (LX and BST) and high current loops.

7. Ground is the return path for the full-load currents flowing into and out of the IC. It is also the common reference

voltage for all analog circuits. Improper ground routing can bring extra resistance and inductance into the current loop,

causing different voltage references and worsening voltage ringing or spikes. Place a solid ground plane layer under

the power loop components layer to shield the switching noise from other sensitive traces. Connect the analog ground

GND and power grounds PGND together at a single point in a star ground connection.

8. The PCB layout also plays an important role in power dissipation and thermal performance. The PGND nodes are the

main power connection area between the IC and the outside of the IC. Place the ground copper area as much as

possible around the PGND area to ensure efficient heat transfer. Place vias as many as possible around the PGND

nodes to further transfer heat down the internal ground plane and other layers, thereby improving the thermal

resistance from the IC package to the ambient.