DM505 datasheet(185/295 Pages) TI2

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DM505

www.ti.com

SPRS976E – NOVEMBER 2016 – REVISED MAY 2018

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Detailed Description

•

Local Enhanced Direct Memory Access (EDMA) controller features:

–

Channel controller (CC) : 64-channel, 128 PaRAM, 2 Queues

–

2 x Third-party Transfer Controllers (TPTC0 and TPTC1):

•

Each TC has a 128-bit read port and a 128-bit write port

•

2KiB FIFOs on each TPTC

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1-dimensional/2-dimensional (1D/2D) addressing

–

Chaining capability

•

DSP subsystem integrated MMUs:

–

Two MMUs are integrated:

•

The MMU0 is located between DSP MDMA master port and the device L3_MAIN interconnect

and can be optionally bypassed

•

The MMU1 is located between the EDMA master port and the device L3_MAIN interconnect

•

A DSP local Power-Down Controller (PDC) is responsible to power-down various parts of the DSP

C66x CorePac, or the entire DSP C66x CorePac.

•

The DSP subsystem System Control logic provides:

–

Slave idle and master standby protocols with device PRCM for powerdown

–

OCP Disconnect handshake for init and target busses

–

Asynchronous reset

–

Power-down modes:

•

"Clockstop" mode featuring wake-up on interrupt event. The DMA event wake-up is managed in

software.

•

The device DSP subsystem is supplied by a PRCM DPLL, but each DSP1/2 has integrated its own

PLL module outside the C66x CorePac for clock gating and division.

•

Each of the two device DSP subsystem has following port instances to connect to remaining part

of the device. See also :

–

A 128-bit initiator (DSP MDMA master) port for MDMA/Cache requests

–

A 128-bit initiator (DSP EDMA master) port for EDMA requests

–

A 32-bit initiator (DSP CFG master) port for configuration requests

–

A 128-bit target (DSP slave) port for requests to DSP memories and various peripherals

•

C66x DSP subsystems (DSPSS) safety aspects:

–

Above mentioned memory ECC/ED mechanisms

–

MMUs enable mapping of only the necessary application space to the processor

–

Memory Protection Units internal to the DSPSS (in L1P, L1D and L2 memory controllers) and

external to DSPSS (firewalls) to help define legal accesses and raise exceptions on illegal

accesses

–

Exceptions: Memory errors, various DSP errors, MMU errors and some system errors are detected

and cause exceptions. The exceptions could be handled by the DSP or by a designated safety

processor at the chip level. Note that it may not be possible for the safety processor to completely

handle some exceptions

Unsupported features on the C66x DSP core for the device are:

•

The Extended Memory Controller MPAX (memory protection and address extension) 36-bit addressing

is NOT supported

Known DSP subsystem power mode restrictions for the device are:

•

"Full logic / RAM retention" mode featuring wake-up on both interrupt or DMA event (logic in “always

on” domain). Only OFF mode is supported by DSP subsystem, requiring full boot.

DM505 Datasheet(PDF) 185 Page - Texas Instruments

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