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TDA2SA Datasheet(PDF) 165 Page - Texas Instruments |
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TDA2SA Datasheet(HTML) 165 Page - Texas Instruments |
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165 / 427 page  165 TDA2SX, TDA2SG, TDA2SA TDA2HG, TDA2HV, TDA2HF, TDA2LF www.ti.com SPRS951F – DECEMBER 2015 – REVISED MAY 2019 Submit Documentation Feedback Product Folder Links: TDA2SX TDA2SG TDA2SA TDA2HG TDA2HV TDA2HF TDA2LF Specifications Copyright © 2015–2019, Texas Instruments Incorporated 5.7.9 Dual Voltage SDIO1833 DC Electrical Characteristics Table 5-16 summarizes the DC electrical characteristics for Dual Voltage SDIO1833 Buffers. Table 5-16. Dual Voltage SDIO1833 DC Electrical Characteristics PARAMETER MIN NOM MAX UNIT Signal Names in Mode 0: mmc1_clk, mmc1_cmd, mmc1_data[3:0] Bottom Balls: W6 / Y6 / AA6 / Y4 / AA5 / Y3 1.8-V Mode VIH Input high-level threshold 1.27 V VIL Input low-level threshold 0.58 V VHYS Input hysteresis voltage 50 (2) mV IIN Input current at each I/O pin 30 µA IOZ IOZ(IPAD Current) for BIDI cell. This current is contributed by the tristated driver leakage + input current of the Rx + weak pullup/pulldown leakage. PAD is swept from 0 to VDDS and the Max(I(PAD)) is measured and is reported as IOZ 30 µA IIN with pulldown enabled Input current at each I/O pin with weak pulldown enabled measured when PAD = VDDS 50 120 210 µA IIN with pullup enabled Input current at each I/O pin with weak pullup enabled measured when PAD = 0 60 120 200 µA CPAD Pad capacitance (including package capacitance) 5 pF VOH Output high-level threshold (IOH = 2 mA) 1.4 V VOL Output low-level threshold (IOL = 2 mA) 0.45 V 3.3-V Mode VIH Input high-level threshold 0.625 × VDDS V VIL Input low-level threshold 0.25 × VDDS V VHYS Input hysteresis voltage 40 (2) mV IIN Input current at each I/O pin 110 µA IOZ IOZ(IPAD Current) for BIDI cell. This current is contributed by the tristated driver leakage + input current of the Rx + weak pullup/pulldown leakage. PAD is swept from 0 to VDDS and the Max(I(PAD)) is measured and is reported as IOZ 110 µA IIN with pulldown enabled Input current at each I/O pin with weak pulldown enabled measured when PAD = VDDS 40 100 290 µA IIN with pullup enabled Input current at each I/O pin with weak pullup enabled measured when PAD = 0 10 100 290 µA CPAD Pad capacitance (including package capacitance) 5 pF VOH Output high-level threshold (IOH = 2 mA) 0.75 × VDDS V VOL Output low-level threshold (IOL = 2 mA) 0.125 × VDDS V (1) VDDS stands for corresponding power supply (that is vddshv8). For more information on the power supply name and the corresponding ball, see Table 4-2, POWER [11] column. (2) Hysteresis is enabled/disabled with CTRL_CORE_CONTROL_HYST_1.SDCARD_HYST register. 5.7.10 Dual Voltage LVCMOS DC Electrical Characteristics Table 5-17 summarizes the DC electrical characteristics for Dual Voltage LVCMOS Buffers. |
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