TDA2SA datasheet(344/427 Pages) TI2

344 / 427 page

Signal

Power

Ground

Signal

SWPS040-200

344

TDA2SX, TDA2SG, TDA2SA

TDA2HG, TDA2HV, TDA2HF, TDA2LF

SPRS951F – DECEMBER 2015 – REVISED MAY 2019

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Product Folder Links: TDA2SX TDA2SG TDA2SA TDA2HG TDA2HV TDA2HF TDA2LF

Applications, Implementation, and Layout

Figure 8-19. Guard Ring Routing

The intention of the guard ring is that HF-energy, that otherwise would have been emitted from the PCB

edge, is reflected back into the board where it partially will be absorbed. For this purpose ground traces on

the borders of all layers (including power layer) must be applied as shown in Figure 8-19.

As these traces must have the same (HF–) potential as the ground plane they must be connected to the

ground plane at least every 10 mm.

8.2.6.3.5 Analog and Digital Ground

For the optimum solution, the AGND and the DGND planes must be connected together at the power

supply source in a same point. This ensures that both planes are at the same potential, while the transfer

of noise from the digital to the analog domain is minimized.

8.3

Core Power Domains

This section provides boundary conditions and theoretical background to be applied as a guide for

optimizing a PCB design. The decoupling capacitor and PDN characteristics tables shown below give

recommended capacitors and PCB parameters to be followed for schematic and PCB designs. Board

designs that meet the static and dynamic PDN characteristics shown in tables below will be aligned to the

expected PDN performance needed to optimize SoC performance.

8.3.1

General Constraints and Theory

•

Max PCB static/DC voltage drop (IRd) budget of 1.5% of supply voltage when using PMICs without

remote sensing as measured from PMIC’s power inductor and filter capacitor node to Processor input

including any ground return losses.

•

Max PCB static/DC voltage drop (IRd) budget can be relaxed to 5% of supply voltage when using

PMICs with remote sensing at the load as measured from PMIC’s power inductor and filter capacitor

node to Device’s supply input including any ground return losses.

•

PMIC component DM and guidelines should be referenced for the following:

–

Routing remote feedback sensing to optimize per each SMPS’s implementation

–

Selecting power filtering capacitor values and PCB placement.

•

Max Effective Resistance (Reff) budget can range from 4 – 50m

Ω for key Device power rails not

including ground returns depending upon maximum load currents and maximum DC voltage drop

budget (as discussed above).

•

Max Device supply input voltage difference budget of 5mV under max current loading shall be

maintained across all balls connected to a common power rail. This represents any voltage difference

that may exist between a remote sense point to any power input.

•

Max PCB Loop Inductance (LL) budget between Device’s power inputs and local bulk and high

frequency decoupling capacitors including ground returns should range from 0.4 – 2.5nH depending

upon maximum transient load currents.

•

Max PCB dynamic/AC peak-to-peak transient noise voltage budgets between PMIC and Device

including ground returns are as follows:

–

+/-3% of nominal supply voltage for frequencies below the PMIC bandwidth (typ Fpmic ~

200kHz)

–

+/-5% of nominal supply voltage for frequencies between Fpmic to Fpcb (typ 20 – 100MHz)

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