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TDA2SA Datasheet(PDF) 347 Page - Texas Instruments

Part # TDA2SA
Description  TDA2x ADAS Applications Processor 23mm Package (ABC Package) Silicon Revision 2.0
PDF  427 Pages
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Manufacturer  TI2 [Texas Instruments]
Direct Link  https://www.ti.com
Logo TI2 - Texas Instruments

TDA2SA Datasheet(HTML) 347 Page - Texas Instruments

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347
TDA2SX, TDA2SG, TDA2SA
TDA2HG, TDA2HV, TDA2HF, TDA2LF
www.ti.com
SPRS951F – DECEMBER 2015 – REVISED MAY 2019
Submit Documentation Feedback
Product Folder Links: TDA2SX TDA2SG TDA2SA TDA2HG TDA2HV TDA2HF TDA2LF
Applications, Implementation, and Layout
Copyright © 2015–2019, Texas Instruments Incorporated
•
LL values shown are the recommended max PCB trace inductance between a decoupling capacitor’s
power supply and ground reference terminals when viewed from the decoupling capacitor with a
“theoretical shorted” applied across the Processor’s supply inputs to ground reference.
•
Z values shown are the recommended max PCB trace impedances allowed between Fpmic up to Fpcb
frequency range that limits transient noise drops to no more than 5% of min supply voltage during max
transient current events.
•
Fpcb (Frequency of Interest) is defined to be a power rail’s max frequency after which adding a
reasonable number of decoupling capacitors no longer significantly reduces the power rail impedance
below the desired impedance target (Zt2). This is due to the dominance of the PCB’s parasitic planar
spreading and internal package inductances.
Table 8-3. Recommended PDN and Decoupling Characteristics (1)(2)(3)(4)(5)
PDN Analysis:
Static
Dynamic
Number of Recommended Decoupling Capacitors
per Supply
Supply
Max Reff
(7)
[mΩ]
Dec. Cap.
Max LL(8) (6)
[nH]
Impedance
[mΩ]
Frequency
of Interest
[MHz]
100
nF(6)
220
nF
470
nF
1 μF
2.2
μF
4.7
μF
10
μF
22 μF
vdd_mpu
10
2
57
20
12
2
2
3
1
1
1
vdd_dspeve
13
2.5
54
20
8
1
1
2
1
1
1
vdd
27
2
87
50
6
1
1
1
1
1
vdd_gpu
18
2.5
207
50
6
1
1
1
1
1
vdd_iva
48
2
800
100
5
1
1
vdds_ddr1
10
2.5
200
100
8
4
2
2
1
vdds_ddr2
10
2.5
200
100
8
4
2
2
1
cap_vbbldo_dspeve
N/A
6
N/A
N/A
1
cap_vbbldo_gpu
N/A
6
N/A
N/A
1
cap_vbbldo_iva
N/A
6
N/A
N/A
1
cap_vbbldo_mpu
N/A
6
N/A
N/A
1
cap_vddram_core1
N/A
6
N/A
N/A
1
cap_vddram_core2
N/A
6
N/A
N/A
1
cap_vddram_core3
N/A
6
N/A
N/A
1
cap_vddram_core4
N/A
6
N/A
N/A
1
cap_vddram_core5
N/A
6
N/A
N/A
1
cap_vddram_dspeve1
N/A
6
N/A
N/A
1
cap_vddram_dspeve2
N/A
6
N/A
N/A
1
cap_vddram_gpu
N/A
6
N/A
N/A
1
cap_vddram_iva
N/A
6
N/A
N/A
1
cap_vddram_mpu1
N/A
6
N/A
N/A
1
cap_vddram_mpu2
N/A
6
N/A
N/A
1
(1) For more information on peak-to-peak noise values, see the Recommended Operating Conditions table of the Specifications chapter.
(2) ESL must be as low as possible and must not exceed 0.5 nH.
(3) The PDN (Power Delivery Network) impedance characteristics are defined versus the device activity (that runs at different frequency)
based on the Recommended Operating Conditions table of the Specifications chapter.
(4) The static drop requirement drives the maximum acceptable PCB resistance between the PMIC or the external SMPS and the processor
power balls.
(5) Assuming that the external SMPS (power IC) feedback sense is taken close to processor power balls.
(6) High-frequency (30 to 70MHz) PCB decoupling capacitors
(7) Maximum Reff from SMPS to Processor.
(8) Maximum Loop Inductance for decoupling capacitor.



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