TDA2SA datasheet(349/427 Pages) TI2

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349

TDA2SX, TDA2SG, TDA2SA

TDA2HG, TDA2HV, TDA2HF, TDA2LF

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SPRS951F – DECEMBER 2015 – REVISED MAY 2019

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Applications, Implementation, and Layout

(4) Refer to the PMIC data manual for the latest TPS659039 specifications

(5) A product’s maximum ambient temperature, thermal system design & heat spreading performance could limit the maximum power

dissipation below the full PMIC capacity in order to not exceed recommended SoC max Tj.

Table 8-5 illustrates the approved and validated power supply connections to the Device for the SMPS

outputs of the TPS65917 PMIC.

Table 8-5. TPS65917 Power Supply Connections

TPS65917

Valid Combination 1:

Valid Combination 2

TPS65917

Current Rating Limitation (1) (3)

SMPS1

vdd_mpu

SMPS1: 3.5A

≤ OPP_NOM (dual

or single) OR

≤ OPP_OD (single

ONLY)

SMPS2 (2)

vdd_dspeve, vdd_gpu, vdd_iva

vdd

3.5A

SMPS3 (2)

vdd

vdd_dspeve, vdd_gpu, vdd_iva

SMPS4 (3)

vdds18v

1.5A

SMPS5 (4)

vdds_ddr1

(1) Refer to the TPS65917 Data Manual for exact current rating limitations, including assumed VIN and other parameters. Values provided in

this table are for comparison purposes.

(2) DSP, EVE, GPU, and IVAHD power consumption is highly application-specific. Separate analysis must be performed to ensure output

current ratings (average and peak) is within the limits of the PMIC. VDD only supports OPP_NOM.

(3) Highly application-specific. Separate analysis must be performed to ensure average and peak power is within the limits of the PMIC.

(4) Furthermore, if SMPS5 is used for DDR power, both total memory + SoC power must be within the PMIC limits.

8.3.6

DPLL Voltage Requirement

The voltage input to the DPLLs has a low noise requirement. Board designs should supply these voltage

inputs with a low noise LDO to ensure they are isolated from any potential digital switching noise. The

TPS65917 and TPS659039 PMIC LDOLN outputs are specifically designed to meet this low noise

requirement.

NOTE

For more information about Input Voltage Sources, see Section 6.3 DPLLs, DLLs

Specifications.

Table 8-4 present the voltage inputs that supply the DPLLs.

Table 8-6. Input Voltage Power Supplies for the DPLLs

POWER SUPPLY

DPLLs

vdda_abe_per

DPLL_PER, DPLL_ABE and PER HSDIVIDER analog power supply

vdda_ddr

DPLL_DDR and DDR HSDIVIDER analog power supply

vdda_debug

DPLL_DEBUG analog power supply

vdda_dsp_eve

DPLL_DSP and DPLL_EVE analog power supply

vdda_gmac_core

DPLL_CORE and HSDIVIDER analog power supply

vdda_gpu

DPLL_GPU analog power supply

vdda_iva

DPLL_IVA analog power supply

vdda_video

DPLL_VIDEO1 and DPLL_VIDEO2 analog power supply

vdda_mpu

DPLL_MPU analog power supply

vdda_osc

not DPLL input but is required to be supplied by low noise input voltage

8.3.7

Loss of Input Power Event

A few key PDN design items needed to enable a controlled and compliant SoC power down sequence for

a “Loss of Input Power” event are:

TDA2SA Datasheet(PDF) 349 Page - Texas Instruments

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